公开(公告)号：US07972694B2

公开(公告)日：2011-07-05

申请号：US12162164

申请日：2006-11-27

Applicant: Mitsuru Sekiguchi ,  Kazuya Tsukada ,  Hisatake Okada

Inventor： Mitsuru Sekiguchi ,  Kazuya Tsukada ,  Hisatake Okada

IPC: B32B5/16

CPC classification number: C09K11/7442 ,  B22F1/0025 ,  B82Y30/00 ,  C01B21/0632 ,  C01G15/00 ,  C01G28/02 ,  C01G30/002 ,  C01P2002/84 ,  C01P2004/16 ,  C01P2004/30 ,  C01P2004/64 ,  C01P2004/84 ,  C01P2006/40 ,  C09K11/62 ,  C22C1/0491 ,  Y10S977/774 ,  Y10S977/813 ,  Y10S977/815 ,  Y10S977/825 ,  Y10S977/832 ,  Y10T428/24942 ,  Y10T428/2933 ,  Y10T428/2991

Abstract: A semiconductor nanoparticle and semiconductor nanorod that have optical characteristics (luminescence intensity and emission lifetime) superior to those of conventional core/shell nanosized semiconductors. There are provided a triple-layer semiconductor nanoparticle, and triple-layer semiconductor nanorod, having an average particle diameter of 2 to 50 nm and comprising a core layer, an interlayer and a shell layer, wherein the layers are composed of different crystals, and wherein the crystal constructing the shell layer exhibits a band gap greater than that of the crystal constructing the core layer, and wherein the crystal constructing the interlayer has a lattice constant assuming a value between those of the crystal constructing the core layer and the crystal constructing the shell layer.

Abstract translation: 具有优于常规核/壳纳米尺寸半导体的光学特性（发光强度和发光寿命）的半导体纳米颗粒和半导体纳米棒。 提供平均粒径为2〜50nm的三层半导体纳米颗粒和三层半导体纳米棒，其包含芯层，中间层和壳层，其中层由不同的晶体构成，并且 其中，构成壳层的晶体的表面带隙大于构成芯层的晶体的带隙，构成中间层的晶体的晶体晶格常数为假定构成芯层的晶体的构成晶格常数与构成芯层的晶体的晶格常数 壳层。

公开(公告)号：US07786447B2

公开(公告)日：2010-08-31

申请号：US11942365

申请日：2007-11-19

Applicant: Masashi Kondo ,  Takehiko Shoji ,  Mitsuru Sekiguchi

Inventor： Masashi Kondo ,  Takehiko Shoji ,  Mitsuru Sekiguchi

IPC: G01T1/20

CPC classification number: G21K4/00

Abstract: A scintillator panel comprising: a radiation-transparent substrate; and a phosphor layer provided on the substrate, the phosphor layer emitting light when irradiated with a radiation, wherein at least one edge of the substrate and at least one edge of the phosphor layer are arranged on a same plane.

Abstract translation: 一种闪烁体面板，包括：辐射透明衬底; 以及设置在所述基板上的荧光体层，所述荧光体层在用辐射照射时发光，其中所述基板的至少一个边缘和所述荧光体层的至少一个边缘布置在同一平面上。

公开(公告)号：US07605085B2

公开(公告)日：2009-10-20

申请号：US11532603

申请日：2006-09-18

Applicant: Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

Inventor： Kazuo Tomita ,  Keiji Hashimoto ,  Yasutaka Nishioka ,  Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Akihisa Iwasaki

IPC: H01L21/311

CPC classification number: H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.

Abstract translation: 在基板上形成的p-SiOC膜中形成第一布线和第一伪布线。 形成p-SiOC膜，在p-SiOC膜上形成盖膜。 在盖膜和p-SiOC膜22中形成包括连接到第一布线和第二布线的通孔的双镶嵌布线。在隔离的通孔的周边上形成有通孔。

公开(公告)号：US20080173824A1

公开(公告)日：2008-07-24

申请号：US11971518

申请日：2008-01-09

Applicant: Mitsuru SEKIGUCHI ,  Takehiko Shoji

Inventor： Mitsuru SEKIGUCHI ,  Takehiko Shoji

IPC: H01R4/00

CPC classification number: G21K4/00 ,  C09K11/616 ,  G01T1/2002 ,  G21K2004/10 ,  H04N5/32

Abstract: A scintillator plate is disclosed comprising on a substrate a metal layer and a phosphor layer capable of emitting light upon exposure to radiation, wherein all of the substrate, the phosphor layer and the metal layer are covered with a moisture-resistant protective film. Also disclosed is a scintillator plate comprising on a metal substrate a phosphor layer capable of emitting light upon exposure to radiation, wherein all of the metal substrate and the phosphor layer are covered with a moisture-resistant protective film.

Abstract translation: 公开了一种闪烁体板，其包括在基板上的金属层和能够在暴露于辐射时发光的荧光体层，其中所有基板，荧光体层和金属层被防潮保护膜覆盖。 还公开了一种闪烁体板，其在金属基板上包括能够在暴露于辐射时发光的荧光体层，其中所有金属基板和荧光体层被防潮保护膜覆盖。

公开(公告)号：US20060163730A1

公开(公告)日：2006-07-27

申请号：US10520816

申请日：2004-04-07

Applicant: Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Yasutaka Nishioka ,  Kazuo Tomita ,  Akihisa Iwasaki ,  Keiji Hashimoto

Inventor： Susumu Matsumoto ,  Mitsuru Sekiguchi ,  Yasutaka Nishioka ,  Kazuo Tomita ,  Akihisa Iwasaki ,  Keiji Hashimoto

IPC: H01L23/52

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/0274 ,  H01L21/3144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76829 ,  H01L21/76835

Abstract: A first nitrogen-containing insulating film is formed under a low dielectric constant film, in which a via hole is formed, with a first nitrogen-non-containing insulating film interposed between the first nitrogen-containing insulating film and the low dielectric constant film. A second nitrogen-containing insulating film is formed over the low dielectric constant film with a second nitrogen-non-containing insulating film interposed therebetween.

Abstract translation: 在第一含氮绝缘膜和低介电常数膜之间插入第一含氮不含绝缘膜的低介电常数膜形成第一含氮绝缘膜，其中形成通孔。 在低介电常数膜上形成第二含氮绝缘膜，其间插入第二含氮不含绝缘膜。

公开(公告)号：US5936886A

公开(公告)日：1999-08-10

申请号：US953995

申请日：1997-10-20

Applicant: Ryosuke Fujio ,  Mitsuru Sekiguchi

Inventor： Ryosuke Fujio ,  Mitsuru Sekiguchi

IPC: H01L21/8247 ,  G11C16/30 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: G11C16/30

Abstract: In a semiconductor memory device comprising a plurality of memory arrays, the memory array is given a predetermined potential from a terminal via a reference line. Further, a plurality of source switches are connected to the memory arrays and the reference line. The source switches selectively transfer the predetermined potential to each of the memory arrays. In this case, each of the source switches includes a transistor having an electrical ability which is determined by a length of the reference line between each source switch and the terminal.When the transistor is formed by a MOS transistor, the above electrical ability is specified by the ON resistance of the MOS transistor. The MOS transistors are designed so that the ON resistance becomes lower as the length of the reference line between the source switch and the terminal becomes longer. At any rate, a substantially constant voltage is supplied to each of the memory arrays irrelevant of the length of the reference line between each source switch and the terminal.

Abstract translation: 在包括多个存储器阵列的半导体存储器件中，存储器阵列经由参考线从端子被给予预定电位。 此外，多个源极开关连接到存储器阵列和参考线。 源开关选择性地将预定电位传输到每个存储器阵列。 在这种情况下，每个源极开关包括具有由每个源极开关和端子之间的参考线​​的长度决定的电能的晶体管。 当晶体管由MOS晶体管形成时，上述电能由MOS晶体管的导通电阻指定。 MOS晶体管被设计成使得当源极开关和端子之间的参考线​​的长度变长时，导通电阻变低。 无论如何，与每个源极开关和端子之间的参考线​​的长度无关地，向每个存储器阵列提供基本恒定的电压。

公开(公告)号：US5780908A

公开(公告)日：1998-07-14

申请号：US751810

申请日：1996-11-19

Applicant: Mitsuru Sekiguchi ,  Michinari Yamanaka

Inventor： Mitsuru Sekiguchi ,  Michinari Yamanaka

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L29/45 ,  H01L23/02

CPC classification number: H01L21/76814 ,  H01L21/28568 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L23/53223 ,  H01L29/456 ,  H01L2924/0002 ,  Y10S257/924

Abstract: Through exposure of the top surface of a tungsten film to plasma of a gas including nitrogen at a temperature of 550.degree. C. or less, a tungsten nitride layer having a structure in which nitrogen atoms and tungsten atoms are bonded is formed in an area in the vicinity of the surface of the tungsten film. Then, an aluminum alloy film is deposited on the tungsten film, thereby forming a metallic interconnection. Since the nitrogen atoms and the tungsten atoms are bonded in the tungsten nitride layer formed by such plasma nitridation, the tungsten nitric layer not only has a good barrier function to prevent the diffusion of other metal atoms but also can be formed in a small thickness. Accordingly, formation of an alloy layer with a high resistance otherwise caused due to counter diffusion during an annealing process and a junction leakage can be avoided.

Abstract translation: 通过在550℃或更低的温度下将钨膜的顶表面暴露于包含氮气的气体的等离子体中，形成具有氮原子和钨原子结合的氮化钨层的区域 钨膜表面附近。 然后，在钨膜上沉积铝合金膜，从而形成金属互连。 由于氮原子和钨原子结合在通过这种等离子体氮化形成的氮化钨层中，因此钨硝酸盐不仅具有良好的屏障功能，以防止其它金属原子的扩散，而且可以形成为小的厚度。 因此，可以避免在退火处理期间由于反扩散而导致的具有高电阻的合金层的形成和结漏电。

公开(公告)号：US5693557A

公开(公告)日：1997-12-02

申请号：US590086

申请日：1996-01-24

Applicant: Shuji Hirao ,  Hisashi Ogawa ,  Yuka Terai ,  Mitsuru Sekiguchi ,  Masanori Fukumoto ,  Isao Miyanaga

Inventor： Shuji Hirao ,  Hisashi Ogawa ,  Yuka Terai ,  Mitsuru Sekiguchi ,  Masanori Fukumoto ,  Isao Miyanaga

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/70

CPC classification number: H01L28/84 ,  H01L21/3213 ,  H01L21/32131 ,  H01L21/76838 ,  Y10S148/014 ,  Y10S438/964

Abstract: A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.

公开(公告)号：US5451261A

公开(公告)日：1995-09-19

申请号：US114144

申请日：1993-09-01

Applicant: Toyokazu Fujii ,  Mikio Nishio ,  Mitsuru Sekiguchi ,  Kazuhiko Hashimoto

Inventor： Toyokazu Fujii ,  Mikio Nishio ,  Mitsuru Sekiguchi ,  Kazuhiko Hashimoto

IPC: C23C14/04 ,  C23C16/04 ,  H01L21/00 ,  H01L21/677 ,  C23C16/00

CPC classification number: H01L21/67167 ,  C23C14/042 ,  C23C16/042 ,  H01L21/67207 ,  H01L21/67225 ,  H01L21/67796 ,  H01L2223/54473 ,  H01L2223/5448 ,  Y10S438/975

Abstract: On a semiconductor substrate, chips to be products and alignment chips located at a portion a part thereof is left out from a peripheral part of the semiconductor substrate are formed. Contact holes and alignment marks are formed at the chips to be products and the alignment chips. Covering the alignment chips with alignment mark cover parts of a substrate holder, a material for metal wiring is deposited on the semiconductor substrate to form a metal film on the substrate. A mask pattern is formed on the metal film using the alignment marks of the alignment chips on which the metal film is not formed.

Abstract translation: 在半导体基板上，形成从半导体基板的周边部分留出的成为产品的芯片和位于其一部分的对准芯片。 在作为产品的芯片和对准芯片上形成接触孔和对准标记。 用衬底保持器的对准标记覆盖部分覆盖对准芯片，在半导体衬底上沉积用于金属布线的材料，以在衬底上形成金属膜。 使用未形成金属膜的取向芯片的对准标记，在金属膜上形成掩模图案。