公开(公告)号：US06954770B1

公开(公告)日：2005-10-11

申请号：US09938166

申请日：2001-08-23

Applicant: David A. Carlson ,  Gregg A. Bouchard ,  Anand Varadharajan ,  Derek S. Brasili

Inventor： David A. Carlson ,  Gregg A. Bouchard ,  Anand Varadharajan ,  Derek S. Brasili

IPC: G06F1/02 ,  G06F7/58

CPC classification number: G06F7/588 ,  G06F7/582 ,  H04L9/0869

Abstract: A random number generator comprising an oscillator with an output signal dependant upon a random source, a sampling device to sample the output signal from the oscillator to obtain a sampled oscillator output, and a fixed frequency clock driven linear feedback shift register (LFSR) communicatively coupled to the sampling device via a digital gate to receive the sampled oscillator output, and to provide a random number at an output of the LFSR. Additionally, the random number generator may comprise an optional mixing function communicatively coupled to the LFSR to read the random number, and to insert the random number into an algorithm to obtain a robust random number.

Abstract translation: 一种随机数发生器，包括具有取决于随机源的输出信号的振荡器，用于对来自振荡器的输出信号进行采样以获得采样的振荡器输出的采样装置以及通信耦合的固定频率时钟驱动的线性反馈移位寄存器（LFSR） 通过数字门到采样装置接收采样的振荡器输出，并在LFSR的输出端提供随机数。 此外，随机数生成器可以包括通信地耦合到LFSR以读取随机数的可选混合功能，并将随机数插入到算法中以获得鲁棒的随机数。

公开(公告)号：US06754739B1

公开(公告)日：2004-06-22

申请号：US09651945

申请日：2000-08-31

Applicant: Richard E. Kessler ,  Michael S. Bertone ,  Gregg A. Bouchard ,  Maurice B. Steinman

Inventor： Richard E. Kessler ,  Michael S. Bertone ,  Gregg A. Bouchard ,  Maurice B. Steinman

IPC: G06F1300

CPC classification number: G06F9/544

Abstract: A method and architecture for improved system resource management and allocation for the processing of request and response messages in a computer system. The resource management scheme provides for dynamically sharing system resources, such as data buffers, between request and response messages or transactions. In particular, instead of simply dedicating a portion of the system resources to requests and the remaining portion to responses, a minimum amount of resources are reserved for responses and a minimum amount for requests, while the remaining resources are dynamically shared between both types of messages. The method and architecture of the present invention allows for more efficient use of system resources, while avoiding deadlock conditions and ensuring a minimum service rate for requests.

Abstract translation: 一种用于改进系统资源管理和分配以在计算机系统中处理请求和响应消息的方法和架构。 资源管理方案提供在请求和响应消息或事务之间动态共享系统资源，例如数据缓冲器。 特别地，不是简单地将系统资源的一部分专用于请求，而将余下的部分用于响应，而是为响应保留最小量的资源和用于请求的最小量，而剩余的资源在两种类型的消息之间动态共享 。 本发明的方法和体系结构允许更有效地利用系统资源，同时避免死锁状况并确保请求的最低服务速率。

公开(公告)号：US10277510B2

公开(公告)日：2019-04-30

申请号：US13565271

申请日：2012-08-02

Applicant: Rajan Goyal ,  Gregg A. Bouchard

Inventor： Rajan Goyal ,  Gregg A. Bouchard

IPC: H04L12/741 ,  G06N5/02 ,  G06F13/16 ,  G06F12/0802 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/00 ,  G06F3/06 ,  G06F11/20 ,  G06F12/126 ,  H04L12/26 ,  H04L29/06 ,  H04L12/747 ,  H04L12/851 ,  H04L12/801 ,  G06F9/50 ,  H04L29/08 ,  G06F9/46 ,  G11C7/10 ,  G06F12/0868

Abstract: In one embodiment, a system includes a data navigation unit configured to navigate through a data structure stored in a first memory to a first representation of at least one rule. The system further includes at least one rule processing unit configured to a) receive the at least one rule based on the first representation of the at least one rule from a second memory to one of the rule processing unit, and b) processing a key using the at least one rule.

公开(公告)号：US20180352557A1

公开(公告)日：2018-12-06

申请号：US15594497

申请日：2017-06-02

Applicant: Tejas M. Bhatt ,  Gregg A. Bouchard ,  Hong Jik Kim ,  Jason D. Zebchuk ,  Ahmed Shahid

Inventor： Tejas M. Bhatt ,  Gregg A. Bouchard ,  Hong Jik Kim ,  Jason D. Zebchuk ,  Ahmed Shahid

IPC: H04W72/12 ,  G06F9/50 ,  G06F3/06

Abstract: Methods and apparatus for a unified baseband architecture. In an exemplary embodiment, an apparatus includes a shared memory having a plurality of access ports and a scheduler that outputs scheduled jobs. Each scheduled job identifies data processing to be performed. The apparatus also includes a plurality of functional elements coupled to the plurality of access ports, respectively, to access the shared memory. Each functional element is operable to retrieve selected data from the shared memory, process the selected data to generate processed data, and store the processed data into the shared memory based on a received scheduled job.

公开(公告)号：US08782287B2

公开(公告)日：2014-07-15

申请号：US10029679

申请日：2001-12-21

Applicant: Gregg A. Bouchard ,  Mauricio Calle ,  Joel R. Davidson ,  Michael W. Hathaway ,  James T. Kirk ,  Christopher Brian Walton

Inventor： Gregg A. Bouchard ,  Mauricio Calle ,  Joel R. Davidson ,  Michael W. Hathaway ,  James T. Kirk ,  Christopher Brian Walton

IPC: G06F15/16 ,  H04L12/56 ,  H04L12/54

CPC classification number: H04L49/9094 ,  H04L45/00 ,  H04L45/60 ,  H04L47/50 ,  H04L49/90 ,  H04L49/9042

Abstract: A packet processing system comprises first processing circuitry for performing a first function, and first memory circuitry coupled to the first processing circuitry for storing received packets, wherein at least a portion of the packets stored by the first memory circuitry are usable by the first processing circuitry in accordance with the first function. The packet processing system further comprises at least second processing circuitry for performing a second function, and at least second memory circuitry coupled to the second processing circuitry for storing at least a portion of the same packets stored in the first memory circuitry, wherein at least a portion of the packets stored in the second memory circuitry are usable by the second processing circuitry in accordance with the second function. In an illustrative embodiment, the first processing circuitry and the second processing circuitry operate in a packet switching device such as a router. In such case, the first processing circuitry and the second processing circuitry operate between a packet network interface and a switch fabric of the packet switching device.

Abstract translation: 分组处理系统包括用于执行第一功能的第一处理电路和耦合到第一处理电路的第一存储器电路，用于存储所接收的分组，其中由第一存储器电路存储的分组的至少一部分可由第一处理电路 按照第一个功能。 分组处理系统还包括用于执行第二功能的至少第二处理电路，以及耦合到第二处理电路的至少第二存储器电路，用于存储存储在第一存储器电路中的相同分组的至少一部分，其中至少一个 存储在第二存储器电路中的分组的部分可以由第二处理电路根据第二功能使用。 在说明性实施例中，第一处理电路和第二处理电路在诸如路由器的分组交换设备中操作。 在这种情况下，第一处理电路和第二处理电路在分组网络接口和分组交换设备的交换结构之间操作。

公开(公告)号：US08719331B2

公开(公告)日：2014-05-06

申请号：US13565459

申请日：2012-08-02

Applicant: Rajan Goyal ,  Gregg A. Bouchard

Inventor： Rajan Goyal ,  Gregg A. Bouchard

IPC: G06F15/16

CPC classification number: H04L63/06 ,  G06F3/0629 ,  G06F3/0647 ,  G06F9/46 ,  G06F9/5016 ,  G06F9/5027 ,  G06F11/203 ,  G06F12/00 ,  G06F12/0207 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/0802 ,  G06F12/0868 ,  G06F12/126 ,  G06F13/16 ,  G06F13/1642 ,  G06N5/02 ,  G06N5/027 ,  G11C7/1075 ,  H04L43/18 ,  H04L45/742 ,  H04L45/745 ,  H04L47/2441 ,  H04L47/39 ,  H04L63/0227 ,  H04L63/0263 ,  H04L63/10 ,  H04L67/10 ,  H04L69/02 ,  H04L69/22 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/14 ,  Y02D10/22

Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. A work product may be migrated between lookup engines to complete the rule matching process. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.

Abstract translation: 分组处理器提供网络架构中分组的规则匹配。 分组处理器包括具有多个查找引擎和相应的片上存储器单元的查找集群复合体。 片上存储器存储与分组数据匹配的规则。 每个查找引擎接收与分组相关联的密钥请求，并且确定规则的子集以与分组数据匹配。 可以在查找引擎之间迁移工作产品以完成规则匹配过程。 作为规则匹配的结果，查找引擎返回指示是否找到匹配的响应消息。

公开(公告)号：US08560475B2

公开(公告)日：2013-10-15

申请号：US11224728

申请日：2005-09-12

Applicant: Muhammad R. Hussain ,  David A. Carlson ,  Gregg A. Bouchard ,  Trent Parker

Inventor： Muhammad R. Hussain ,  David A. Carlson ,  Gregg A. Bouchard ,  Trent Parker

IPC: G06F17/00

CPC classification number: G06F17/30516 ,  G06F9/4498 ,  G06F17/30958 ,  G06F17/30985

Abstract: An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different interpretations. By generating state for the node, the graph of nodes does not become exponential. It also allows a user function to be called upon reaching a node, which can perform any desired user tasks, including modifying the input data or position.

Abstract translation: 改进的内容搜索机制使用包括智能节点的图避免了后处理的开销，并提高了内容处理应用的整体性能。 智能节点类似于DFA图中的节点，但包含一个命令。 智能节点中的命令允许生成和检查节点的附加状态。 这种附加状态允许内容搜索机制以两种不同的解释遍历相同的节点。 通过生成节点的状态，节点的图形不会变成指数。 它还允许在到达节点时调用用户功能，节点可以执行任何所需的用户任务，包括修改输入数据或位置。

公开(公告)号：US08392590B2

公开(公告)日：2013-03-05

申请号：US11221408

申请日：2005-09-07

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

IPC: G06F15/16 ,  G06F17/28

CPC classification number: H04L49/90 ,  G06F15/7846 ,  H04L29/06 ,  H04L63/02 ,  H04L63/04 ,  H04L63/145 ,  H04L63/164 ,  H04L69/12

Abstract: A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.

Abstract translation: 用于实时传入传入分组数据的运行确定性有限自动机（DFA）图的处理器。 所述处理器包括至少一个处理器核心和与所述至少一个处理器核心异步操作的DFA模块，用于使用存储在高速缓存相干存储器中的分组数据遍历存储在非高速缓冲存储器中的至少一个DFA图形。

公开(公告)号：US20130036471A1

公开(公告)日：2013-02-07

申请号：US13565406

申请日：2012-08-02

Applicant: Gregg A. Bouchard ,  Rajan Goyal ,  Gregory E. Lund

Inventor： Gregg A. Bouchard ,  Rajan Goyal ,  Gregory E. Lund

IPC: G06F21/00

CPC classification number: H04L63/06 ,  G06F3/0629 ,  G06F3/0647 ,  G06F9/46 ,  G06F9/5016 ,  G06F9/5027 ,  G06F11/203 ,  G06F12/00 ,  G06F12/0207 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/0802 ,  G06F12/0868 ,  G06F12/126 ,  G06F13/16 ,  G06F13/1642 ,  G06N5/02 ,  G06N5/027 ,  G11C7/1075 ,  H04L43/18 ,  H04L45/742 ,  H04L45/745 ,  H04L47/2441 ,  H04L47/39 ,  H04L63/0227 ,  H04L63/0263 ,  H04L63/10 ,  H04L67/10 ,  H04L69/02 ,  H04L69/22 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/14 ,  Y02D10/22

Abstract: In one embodiment, a system includes a format block configured to receive a key, at least one rule, and rule formatting information. The rule can have one or more dimensions. The format block can be further configured to extract each of the dimensions from the at least one rule. The system can further include a plurality of dimension matching engines (DME). Each DME can be configured to receive the key and a corresponding formatted dimension, and process the key and the corresponding dimension for returning a match or nomatch. The system can further include a post processing block configured to analyze the matches or no matches returned from the DMEs and return a response based on the returned matches or nomatches.

Abstract translation: 在一个实施例中，系统包括被配置为接收密钥，至少一个规则和规则格式化信息的格式块。 规则可以有一个或多个维。 格式块可以进一步配置为从至少一个规则中提取每个维度。 该系统还可以包括多个尺寸匹配引擎（DME）。 可以将每个DME配置为接收密钥和对应的格式化维度，并处理密钥和相应的维度以返回匹配或nomatch。 该系统还可以包括后处理块，其被配置为分析匹配或者不从DME返回的匹配，并且基于返回的匹配或缩略返回响应。

公开(公告)号：US20130036284A1

公开(公告)日：2013-02-07

申请号：US13565743

申请日：2012-08-02

Applicant: Najeeb I. Ansari ,  Gregg A. Bouchard ,  Rajan Goyal ,  Jeffrey A. Pangborn

Inventor： Najeeb I. Ansari ,  Gregg A. Bouchard ,  Rajan Goyal ,  Jeffrey A. Pangborn

IPC: G06F12/02

CPC classification number: H04L63/06 ,  G06F3/0629 ,  G06F3/0647 ,  G06F9/46 ,  G06F9/5016 ,  G06F9/5027 ,  G06F11/203 ,  G06F12/00 ,  G06F12/0207 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/0802 ,  G06F12/0868 ,  G06F12/126 ,  G06F13/16 ,  G06F13/1642 ,  G06N5/02 ,  G06N5/027 ,  G11C7/1075 ,  H04L43/18 ,  H04L45/742 ,  H04L45/745 ,  H04L47/2441 ,  H04L47/39 ,  H04L63/0227 ,  H04L63/0263 ,  H04L63/10 ,  H04L67/10 ,  H04L69/02 ,  H04L69/22 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/14 ,  Y02D10/22

Abstract: A method and corresponding apparatus of managing transport operations between a first memory cluster and one or more other memory clusters, include selecting, at a clock cycle in the first memory cluster, at least one transport operation destined to at least one destination memory cluster, from one or more transport operations, based at least in part on priority information associated with the one or more transport operations or current states of available processing resources allocated to the first memory cluster in each of a subset of the one or more other memory clusters, and initiating the transport of the selected at least one transport operation.

Abstract translation: 一种管理第一存储器集群与一个或多个其他存储器集群之间的传输操作的方法和相应的装置包括：在第一存储器集群中的时钟周期选择至少一个目的地为至少一个目的地存储器集群的传输操作， 至少部分地基于与一个或多个其他存储器簇的子集中的每一个中分配给第一存储器簇的一个或多个传输操作或可用处理资源的当前状态相关联的优先级信息，以及 启动所选择的至少一个传送操作的传输。