公开(公告)号：US20110309495A1

公开(公告)日：2011-12-22

申请号：US13004936

申请日：2011-01-12

申请人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

发明人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Jar-Dar Yang ,  Yi-Chang Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

摘要翻译： 多芯片堆叠封装结构包括：衬底，其具有限定在其上表面上的芯片放置区域和布置在芯片放置区域外部的多个触点; 第一芯片设置在具有后表面的芯片布置区域中，多个第一焊盘设置在有源表面上，并且多个第一凸块各自形成在第一焊盘之一上; 多个金属线将第一凸块连接到触点; 具有多个第二焊盘的第二芯片设置在所述有源表面上，并且多个第二凸块各自形成在所述第二焊盘之一上，所述第二芯片安装到所述第一芯片，其有源表面面向所述第二焊盘的有效表面 第一芯片，其中所述第二凸块分别对应地连接所述金属线和所述第一凸块。

公开(公告)号：US20110180274A1

公开(公告)日：2011-07-28

申请号：US12695110

申请日：2010-01-27

申请人： David Wei Wang ,  Gary L. Rytlewski

发明人： David Wei Wang ,  Gary L. Rytlewski

IPC分类号： E21B33/12

CPC分类号： E21B23/02 ,  E21B34/14

摘要： An apparatus and method for plugging a wellbore completion. The apparatus includes a body and a variable diameter ring. The body includes a first portion having a first diameter, and a second portion having a second diameter that is smaller than the first diameter. The variable diameter ring is disposed around the body and slidable on the first and second portions. The ring is configured to engage a flow path reduction device when located on the first portion, and to move past the flow path reduction device when located on the second portion.

摘要翻译： 一种用于堵塞井眼完井的装置和方法。 该装置包括主体和可变直径环。 主体包括具有第一直径的第一部分和具有小于第一直径的第二直径的第二部分。 可变直径环设置在主体周围并可在第一和第二部分上滑动。 环被配置为当位于第一部分上时接合流路减小装置，并且当位于第二部分上时移动通过流路减小装置。

公开(公告)号：US07973310B2

公开(公告)日：2011-07-05

申请号：US12501100

申请日：2009-07-10

申请人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

发明人： David Wei Wang ,  An-Hong Liu ,  Hao-Yin Tsai ,  Hsiang-Ming Huang ,  Yi-Chang Lee ,  Shu-Ching Ho

IPC分类号： H01L23/58

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.

摘要翻译： 提供半导体封装结构及其制造方法。 半导体封装结构包括衬底单元和第一芯片堆叠结构。 衬底单元包括具有测试焊盘的电路结构。 第一芯片堆叠结构包括芯片，并且每个芯片具有多个通硅插头。 两个相邻芯片的贯穿硅插头电连接并且进一步电连接到用于电测试的衬底单元的测试焊盘。 由本发明提供的另一半导体封装结构包括第一半导体芯片和第二半导体芯片。 每个半导体芯片具有用于电测试的测试焊盘和连接到测试焊盘的多个穿硅插头。 第二半导体芯片安装在第一半导体芯片上，并且两个半导体芯片的贯穿硅插头的一部分彼此电连接。

公开(公告)号：US20080308916A1

公开(公告)日：2008-12-18

申请号：US12198536

申请日：2008-08-26

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L23/495 ,  H01L23/49

CPC分类号： H01L23/4951 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49575 ,  H01L24/31 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/05599

摘要： A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the carrier and a first active surface of the first chip to electrically connect with the first chip and the carrier. The bonding wires pass through the opening of the carrier and are electrically connected with the carrier and the second chip. The first adhesive layer adhered between the first active surface of the first chip and the carrier includes a first B-staged adhesive layer adhered on the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the carrier.

摘要翻译： 提供了包括具有开口的载体，第一芯片，凸块，第二芯片，接合线，第一粘合层和模塑料的芯片封装。 第一芯片和第二芯片设置在载体的相对两侧。 凸块设置在载体和第一芯片的第一有源表面之间以与第一芯片和载体电连接。 接合线穿过载体的开口并与载体和第二芯片电连接。 附着在第一芯片的第一活性表面和载体之间的第一粘合剂层包括附着在第一芯片的第一有源表面上的第一B阶粘合剂层和粘附在第一B层之间的第二B阶粘合剂层 粘合剂层和载体。

公开(公告)号：US20080268572A1

公开(公告)日：2008-10-30

申请号：US12169132

申请日：2008-07-08

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L21/58

CPC分类号： H01L24/16 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

摘要翻译： 提供了芯片封装结构的制造工艺。 首先，提供具有多个第一接合焊盘的第一基板和具有多个第二接合焊盘的第二基板，其中在第一基板的第一接合焊盘上形成多个凸点。 在第一基板上或第二基板上形成第一两级粘合剂层，并且被B阶段化以形成第一B阶粘合剂层。 在第一B阶粘合剂层上形成第二两层粘合剂层，并且被B阶段化以形成第二B阶粘合剂层。 然后，第一基板和第二基板经由第一B阶粘合剂层和第二B阶粘合剂层接合，使得每个第一接合焊盘分别经由第一接合焊盘中的一个电连接到第二接合焊盘中的一个 颠簸

公开(公告)号：US20070104124A1

公开(公告)日：2007-05-10

申请号：US11269414

申请日：2005-11-08

申请人： Jonathan Lee ,  Gregory Youngblood ,  David (Wei) Wang

发明人： Jonathan Lee ,  Gregory Youngblood ,  David (Wei) Wang

IPC分类号： G08C17/00

CPC分类号： H04L12/10

摘要： Certain embodiments of a cable sense mode for intelligent power saving in the absence of a link pulse may include detecting an energy level of an Ethernet link. The Ethernet link may couple a network adapter chip to a network. The power supplied to the network adapter chip may be adjusted based on the detected energy level. Power may be supplied to the network adapter chip if the detected energy level of the Ethernet link is greater than or equal to a particular energy level. Power may be reduced to the network adapter chip if the detected energy level of the Ethernet link is less than a particular energy level. An output signal and/or an interrupt signal may be generated that indicates a change in the detected energy level of the Ethernet link. Power may be provided to the circuitry that generates the output signal and the interrupt signal.

摘要翻译： 在没有链路脉冲的情况下用于智能省电的电缆感测模式的某些实施例可以包括检测以太网链路的能量级别。 以太网链路可能将网络适配器芯片耦合到网络。 可以基于检测到的能量水平来调整提供给网络适配器芯片的功率。 如果检测到的以太网链路的能量级别大于或等于特定能级，则可以向网络适配器芯片供电。 如果检测到的以太网链路的能量级别小于特定的能级，则电源可能会减少到网络适配器芯片。 可以生成指示以太网链路检测到的能级的变化的输出信号和/或中断信号。 可以向产生输出信号和中断信号的电路提供功率。

公开(公告)号：US07147054B2

公开(公告)日：2006-12-12

申请号：US10654101

申请日：2003-09-03

申请人： David Wei Wang ,  Bruno Khan ,  Michael D. Langlais

发明人： David Wei Wang ,  Bruno Khan ,  Michael D. Langlais

IPC分类号： E21B43/04 ,  E21B43/08

CPC分类号： E21B43/045 ,  E21B17/18 ,  E21B34/063

摘要： A technique that is usable with a subterranean well includes communicating a slurry through a shunt flow path and operating a control device to isolate slurry from being communicated to an ancillary flow path. The system may include a shunt tube and a diverter. The shunt tube is adapted to communicate a slurry flow within the well to form a gravel pack. The diverter is located in a passageway of the shunt tube to divert at least part of the flow. A slurry may be communicated through the shunt flow path, and a control device may be operated to isolate the slurry from being communicated to the ancillary flow path.

摘要翻译： 可与地下井一起使用的技术包括通过分流流动路径传送浆料并操作控制装置以分离浆料与辅助流动路径的连通。 该系统可以包括分流管和分流器。 分流管适于将井内的浆料流通过以形成砾石包装。 分流器位于分流管的通道中以转移至少部分流动。 浆料可以通过分流流路连通，并且可以操作控制装置以隔离浆料与辅助流动路径的连通。

公开(公告)号：US5656862A

公开(公告)日：1997-08-12

申请号：US59003

申请日：1993-05-06

申请人： Kostas I. Papathomas ,  David Wei Wang

发明人： Kostas I. Papathomas ,  David Wei Wang

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/29 ,  H05K3/28 ,  H05K3/34 ,  H01L23/48 ,  H01L29/40 ,  H01L39/02

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/293 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/83856 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/284 ,  H05K3/285 ,  H05K3/3431 ,  Y10T428/31504 ,  Y10T428/31547

摘要： Solder interconnection encapsulant, encapsulated structure and method for its fabrication and use, whereby the gap created by solder connections between a carrier substrate and a semiconductor device is filled with a composition obtained from curing a preparation containing a cycloaliphatic polyepoxide and/or curable cyanate ester or prepolymer thereof; filler, e.g., an aluminum nitride or aluminum oxide filler, having a maximum particle size of 31 microns.

摘要翻译： 焊接互连密封剂，封装结构及其制造和使用方法，由此通过固化含有脂环族聚环氧化物和/或可固化氰酸酯的制剂获得的组合物填充载体基底和半导体器件之间的焊料连接所产生的间隙，或 其预聚物; 填料，例如氮化铝或氧化铝填料，其最大粒度为31微米。

公开(公告)号：US20110291267A1

公开(公告)日：2011-12-01

申请号：US12856754

申请日：2010-08-16

申请人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yi-Chang Lee

发明人： David Wei Wang ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yi-Chang Lee

IPC分类号： H01L23/498

CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip stack package structure can be enhanced with the application of these soft metal caps.

摘要翻译： 半导体晶片结构包括第一表面和与第一表面相对的第二表面，形成在第一表面上的多个芯片区域，多个通孔形成在多个芯片区域中的每一个中，所述多个芯片区域连接第一表面和 第二表面和形成在每个贯通硅孔中的贯通硅通孔（TSV）电极结构。 每个贯通硅通孔电极结构包括形成在通孔的内壁上的电介质层，形成在电介质层的内壁上并在其中限定空位的阻挡层，填充到空位中的填充金属层 ，所述填充金属层的第一端低于形成凹部的第一表面;以及连接到所述填充金属层的第一端并覆盖所述填充金属层的第一端的软金属帽，其中所述软金属帽的一部分形成在所述凹部 并且软金属帽从第一表面突出。 因此，通过应用这些软金属盖，可以提高多芯片堆叠封装结构的可靠性。

公开(公告)号：US07960214B2

公开(公告)日：2011-06-14

申请号：US12169132

申请日：2008-07-08

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L21/44

CPC分类号： H01L24/16 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

摘要翻译： 提供了芯片封装结构的制造工艺。 首先，提供具有多个第一接合焊盘的第一基板和具有多个第二接合焊盘的第二基板，其中在第一基板的第一接合焊盘上形成多个凸点。 在第一基板上或第二基板上形成第一两级粘合剂层，并且被B阶段化以形成第一B阶粘合剂层。 在第一B阶粘合剂层上形成第二两层粘合剂层，并且被B阶段化以形成第二B阶粘合剂层。 然后，第一基板和第二基板经由第一B阶粘合剂层和第二B阶粘合剂层接合，使得每个第一接合焊盘分别经由第一接合焊盘中的一个电连接到第二接合焊盘中的一个 颠簸