公开(公告)号：US11742276B2

公开(公告)日：2023-08-29

申请号：US17725527

申请日：2022-04-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Li-Huan Chu ,  Hsu-Hsien Chen ,  Liang-Chen Lin ,  Tsung-Yang Hsieh ,  Hsin-Hsien Lee ,  Kuen-Hong Tsai

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/76 ,  H01L29/04 ,  H01L21/02 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L21/60

CPC分类号： H01L23/49827 ,  H01L21/02433 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76 ,  H01L21/768 ,  H01L23/49866 ,  H01L23/538 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/045 ,  H01L2021/60135 ,  H01L2224/81815 ,  H01L2225/06555 ,  H01L2225/06562

摘要： A package manufacturing process and semiconductor packages are provided. An interposer having a crystal structure is provided. A first die and a second die are bonded on the interposer. The second die is positioned to be spaced apart from the first die with a gap extending direction that is perpendicular to a shortest distance of the gap, and the gap extending direction is not parallel with a crystallographic orientation of the crystal structure of the interposer. A molding compound is formed over the interposer covering the first and second dies. The molding compound and the interposer are cut into packages.

公开(公告)号：US11742216B2

公开(公告)日：2023-08-29

申请号：US17005021

申请日：2020-08-27

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Tae Ho Yoon ,  Yang Gyoo Jung ,  Min Ho Kim ,  Youn Seok Song ,  Dong Soo Ryu ,  Choong Hoe Kim

IPC分类号： H01L21/48 ,  H01L23/00 ,  G02B27/09 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/60

CPC分类号： H01L21/4853 ,  G02B27/0927 ,  H01L24/75 ,  H01L24/81 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/60112 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/75263 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/131 ,  H01L2924/014

摘要： A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate.

公开(公告)号：US20230071960A1

公开(公告)日：2023-03-09

申请号：US17447041

申请日：2021-09-07

申请人： STATS ChipPAC Pte. Ltd.

发明人： Bokyeong Hwang ,  Jingwan Kim ,  Minjung Kim

IPC分类号： H01L23/051 ,  H01L23/049 ,  H01L21/60

摘要： A semiconductor device has a substrate and a first semiconductor die disposed over the substrate. A first metal frame is disposed over the substrate around the first semiconductor die. A first metal lid is disposed over the first metal frame. A flap of the first metal lid includes an elastic characteristic to latch onto the first metal frame. An edge of the flap can have a castellated edge. A recess in the first metal frame and a protrusion on the first metal lid can be used to latch the first metal lid onto the first metal frame. A second metal frame and second metal lid can be disposed over an opposite surface of the substrate from the first metal frame.

公开(公告)号：US11600498B2

公开(公告)日：2023-03-07

申请号：US16732293

申请日：2019-12-31

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： James Raymond Maliclic Baello ,  Steffany Ann Lacierda Moreno

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/29 ,  H01L21/48 ,  H01L21/60

摘要： A semiconductor package includes a leadframe forming a plurality of leads with a die attach site, a semiconductor die including a set of die contacts mounted to the die attach site in a flip chip configuration with each die contact of the set of die contacts electrically connected to leadframe via one of a set of solder joints, a set of solder joint capsules covering each of the set of solder joints against the leadframe, a clip mounted to the leadframe over the semiconductor die with a clip solder joint. The solder joint capsules restrict flow of the solder joints of the semiconductor die contacts in the flip chip configuration such that the solder remains in place if remelted during later clip solder reflow.

公开(公告)号：US11587879B2

公开(公告)日：2023-02-21

申请号：US17141922

申请日：2021-01-05

申请人： FUJI ELECTRIC CO., LTD.

发明人： Naoki Takizawa

IPC分类号： H01L23/52 ,  H01L23/538 ,  H01L21/50 ,  H01L23/532 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/373 ,  H05K1/03 ,  H01L21/60 ,  H05K3/24

摘要： An electronic device includes a first part, and a circuit plate including a circuit substrate, a plating film made of a plating material and being disposed on a front surface of the substrate. The plating film includes a first part region on which the first part is disposed via a first solder, and a liquid-repellent region extending along a periphery side of the first part region in a surface layer of the plating film, and having a liquid repellency greater than a liquid repellency of the plating film. The liquid-repellent region includes a resist region. The plating film includes a remaining portion between the liquid-repellent region and the front surface of the circuit substrate in a thickness direction of the plating film orthogonal to the front surface. The remaining portion is made of the plating material and is free of the oxidized plating material.

公开(公告)号：US11582865B2

公开(公告)日：2023-02-14

申请号：US17313006

申请日：2021-05-06

申请人： InnoLux Corporation

发明人： Yeong-E Chen ,  Cheng-En Cheng ,  Yu-Ting Liu

IPC分类号： H05K3/22 ,  H05K3/24 ,  H05K3/46 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L21/66 ,  H01L23/31 ,  H01L23/485 ,  H05K1/02 ,  H05K3/02

摘要： A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer including a first dielectric layer, a conductive layer, and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test mark, the test mark includes a plurality of conductive patterns formed of the conductive layer, and the conductive patterns are arranged in a ring shape.

公开(公告)号：US11557531B2

公开(公告)日：2023-01-17

申请号：US17264945

申请日：2019-09-24

申请人： Mitsubishi Electric Corporation

发明人： Shohei Ogawa ,  Junji Fujino ,  Yusuke Ishiyama ,  Isao Oshima ,  Takumi Shigemoto

IPC分类号： H01L21/50 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L21/60

摘要： A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.

公开(公告)号：US11527496B2

公开(公告)日：2022-12-13

申请号：US16890613

申请日：2020-06-02

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Jong Sik Paek ,  Won Chul Do ,  Doo Hyun Park ,  Eun Ho Park ,  Sung Jae Oh

IPC分类号： H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/367 ,  H01L21/60

摘要： A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

公开(公告)号：US11521935B2

公开(公告)日：2022-12-06

申请号：US17227811

申请日：2021-04-12

申请人： Applied Materials, Inc.

发明人： Han-Wen Chen ,  Steven Verhaverbeke ,  Giback Park ,  Giorgio Cellere ,  Diego Tonini ,  Vincent Dicaprio ,  Kyuil Cho

IPC分类号： H01L23/495 ,  H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/10 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H05K1/02 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065 ,  H01L27/06 ,  H01L21/60

摘要： The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

公开(公告)号：US11515258B2

公开(公告)日：2022-11-29

申请号：US17026793

申请日：2020-09-21

申请人： Zhuhai ACCESS Semiconductor Co., Ltd

发明人： Xianming Chen ,  Yejie Hong ,  Benxia Huang ,  Lei Feng

IPC分类号： H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L23/15 ,  H01L23/00 ,  H01L21/60

摘要： A method for manufacturing a package substrate, includes: providing a glass frame having a through hole and a chip embedding cavity; fixing an electronic component in the chip embedding cavity; coating a dielectric layer to an upper surface of the glass frame, the through hole and the chip embedding cavity and curing the dielectric layer; photoetching the dielectric layer to form an opening window arranged above the through hole; depositing metal through the opening window and patterning the metal to form a metal pillar and a circuit layer, the metal pillar passing through the through hole, the circuit layer being arranged on the upper surface and/or a lower surface of the glass frame and being connected to the electronic component and the metal pillar; forming a solder mask on a surface of the circuit layer, patterning the solder mask to form a pad connected to the circuit layer.