公开(公告)号：US12178046B2

公开(公告)日：2024-12-24

申请号：US18347973

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Yong Seok Kim ,  Kyung Hwan Lee ,  Jun Hee Lim ,  Jee Hoon Han

IPC: H10B43/27 ,  G11C16/04 ,  G11C16/08 ,  H01L23/528 ,  H01L25/00 ,  H01L25/18 ,  H01L29/10 ,  H01L29/78 ,  H10B43/40

Abstract: A semiconductor device includes a lower stack structure that includes a lower word line, an upper stack structure that is on the lower stack structure and includes an upper word line, a decoder that is adjacent to the lower stack structure and the upper stack structure, a signal interconnection that is connected to the decoder, a lower selector that is connected to the signal interconnection and further connected to the lower word line, and an upper selector that is connected to the signal interconnection, isolated from direct contact with the lower selector, and further connected to the upper word line.

公开(公告)号：US12176036B2

公开(公告)日：2024-12-24

申请号：US17881352

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sara Choi ,  Hyunkook Park

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/20 ,  G11C16/26

Abstract: A memory device and an operating method thereof adjust a slope of a word line voltage. The memory device includes a memory cell array including a plurality of cell strings, a voltage generating circuit configured to generate a word line voltage provided to a plurality of word lines, and a control logic configured to output a slope control signal adjusting a voltage level variation characteristic of the word line voltage provided from the voltage generating circuit, wherein, during a prepulse period of a read operation of the memory device, a slope of a first word line voltage provided to an edge group including one or more word lines, the edge group adjacent to a string selection line is greater than a slope of a second word line voltage provided to a center group including one or more word lines in a center region.

公开(公告)号：US12176033B2

公开(公告)日：2024-12-24

申请号：US17951794

申请日：2022-09-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhipeng Dong ,  Ying Cui ,  Li Xiang

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/14

Abstract: A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a peripheral circuit. The memory string includes a memory cell and a select transistor including a storage layer. The word line is coupled to the memory cell. The select line is coupled to the select transistor. The peripheral circuit is coupled to the SL, the BL, the select line, and the word line. The peripheral circuit is configured to: apply a first voltage to the select line; and apply a second voltage to the SL and/or the BL, in which a first peak level of the first voltage is greater than a second peak level of second voltage.

公开(公告)号：US20240420794A1

公开(公告)日：2024-12-19

申请号：US18624904

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youhwan Kim ,  Sewoong Lee ,  Haedong No ,  Ho-Sung Ahn ,  Youn-Soo Cheon

IPC: G11C29/52 ,  G11C16/08 ,  G11C29/50

Abstract: A non-volatile memory device comprises a memory cell array comprising a plurality of memory cell blocks; and an address decoder connected to the memory cell array through a plurality of word lines and configured to apply a read pass voltage to unselected word lines of a selected memory cell block among the plurality of memory cell blocks and apply the read pass voltages of different levels to different memory cell blocks among the plurality of memory cell blocks.

公开(公告)号：US12165712B2

公开(公告)日：2024-12-10

申请号：US18362221

申请日：2023-07-31

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada ,  Shohei Asami ,  Masamichi Fujiwara

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

公开(公告)号：US12165711B2

公开(公告)日：2024-12-10

申请号：US18228166

申请日：2023-07-31

Applicant: Kioxia Corporation

Inventor： Kosuke Yanagidaira ,  Hiroshi Tsubouchi

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.

公开(公告)号：US12165692B2

公开(公告)日：2024-12-10

申请号：US17402404

申请日：2021-08-13

Applicant: Micron Technology, Inc.

Inventor： Michele Piccardi

IPC: G11C16/08 ,  G11C11/4074 ,  G11C11/408 ,  G11C16/26 ,  G11C16/34

Abstract: Systems and methods of dynamically calibrating memory control signals during increase of wordline voltage for memory technologies subject to charge loss are disclosed. In one aspect, an exemplary method may comprise using an internal node, such as a wordline regulator output or return feedback line or a replica of the wordline, as proxy for the local wordline voltage. In one or more further embodiments, the proxy signal may be converted to digital signal or code and even determined in the background before the signal is needed for calibration. As a function of the disclosed technology, calibration of memory control signals, such as pass voltage and wordline read-verify voltage, may be performed during increase of the wordlines voltage with no impact or penalty on read/program time.

公开(公告)号：US12160999B2

公开(公告)日：2024-12-03

申请号：US17579640

申请日：2022-01-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H10B99/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/06 ,  H01L27/12 ,  H10B12/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/70

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

公开(公告)号：US20240395329A1

公开(公告)日：2024-11-28

申请号：US18793392

申请日：2024-08-02

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou ,  Murong Lang

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10

Abstract: A method includes determining a boundary word line in a partial block of a flash memory device, where the partial block includes blank word lines after the boundary word line; determining a single predefined level of pure data to write in at least one of the blank word lines after the boundary word line; and writing the single predefined level of pure data to at least one of the blank word lines after the boundary word line.

公开(公告)号：US20240395328A1

公开(公告)日：2024-11-28

申请号：US18790609

申请日：2024-07-31

Applicant: Sandisk Technologies, Inc.

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.