知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.018 seconds)

    Memory system
    3.
    发明授权
    Memory system 有权

    公开(公告)号：US11756642B2

    公开(公告)日：2023-09-12

    申请号：US17476229

    申请日：2021-09-15

    Applicant: Kioxia Corporation

    Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Kiwamu Watanabe ,  Kengo Kurose

    IPC: G11C29/12 ,  G11C16/26 ,  G11C16/08 ,  G06F3/06

    CPC classification number: G11C29/12 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0673 ,  G11C16/08 ,  G11C16/26 ,  G11C2029/1202

    Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

    Memory system
    7.
    发明授权
    Memory system 有权

    公开(公告)号：US11626167B2

    公开(公告)日：2023-04-11

    申请号：US17131026

    申请日：2020-12-22

    Applicant: KIOXIA CORPORATION

    Inventor： Masanobu Shirakawa ,  Tsukasa Tokutomi ,  Marie Takada

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/1157

    Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

    Method of controlling a semiconductor memory
    8.
    发明授权
    Method of controlling a semiconductor memory 有权

    公开(公告)号：US11315643B2

    公开(公告)日：2022-04-26

    申请号：US16892817

    申请日：2020-06-04

    Applicant: KIOXIA CORPORATION

    Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa

    IPC: G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G11C16/10 ,  G11C16/04

    Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

    Memory system
    9.
    发明授权
    Memory system 有权

    公开(公告)号：US11211138B2

    公开(公告)日：2021-12-28

    申请号：US17003937

    申请日：2020-08-26

    Applicant: KIOXIA CORPORATION

    Inventor： Tsukasa Tokutomi ,  Kiwamu Watanabe ,  Yuko Noda

    IPC: G11C29/50 ,  G11C29/42 ,  G11C29/44 ,  G11C16/08 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

    Abstract: A memory system includes a memory chip and a memory controller. The memory chip has a first plane and a second plane. A threshold voltage corresponding to multiple bit data is set for each of the memory cells. The memory controller causes the memory chip to execute a first read process on the first plane and the second plane in parallel by using a plurality of first read voltages different from each other for the first plane and the second plane. The first read process being a process of reading a data group of one bit among the multiple bits by using the first read voltages. The memory controller subsequently adjusts the voltage levels of the first read voltages on the basis of the data group read from the memory cells of the first plane and the data group read from the memory cells of the second plane.

Patent Agency Ranking