公开(公告)号：US12068316B2

公开(公告)日：2024-08-20

申请号：US17388005

申请日：2021-07-29

Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wang Jhan ,  Fu-Che Lee ,  Huixian Lai ,  Yu-Cheng Tung ,  An-Chi Liu ,  Gang-Yi Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/7842

Abstract: The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

公开(公告)号：US12068202B2

公开(公告)日：2024-08-20

申请号：US17244410

申请日：2021-04-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sunhom Steve Paak ,  Xiaolong Ma ,  Yanxiang Liu ,  Daxiang Wang ,  Zanfeng Chen ,  Yu Xia ,  Huabin Chen ,  Yongjie Zhou

IPC: H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823481 ,  H01L21/0259 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. A part that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.

公开(公告)号：US20240274606A1

公开(公告)日：2024-08-15

申请号：US18646277

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Sen-Hong Syue ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the fist insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

公开(公告)号：US20240274472A1

公开(公告)日：2024-08-15

申请号：US18637723

申请日：2024-04-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： HSIH-YANG CHIU

IPC: H01L21/8234 ,  H01L21/761 ,  H01L23/00

CPC classification number: H01L21/823481 ,  H01L21/761 ,  H01L21/823475 ,  H01L24/80 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method for manufacturing a semiconductor device structure including a doped region under an isolation feature. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate comprises a first well region with a first conductive type; forming an isolation feature extending from the second surface of the substrate; forming a first transistor and a second transistor adjacent to the second surface of the substrate; forming a first doped region under the isolation feature, wherein the first doped region has a second conductive type different from the first conductive type; and providing a circuit structure on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled with the first doped region.

公开(公告)号：US12062693B2

公开(公告)日：2024-08-13

申请号：US17459748

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first gate electrode layer, a second gate electrode layer disposed over and aligned with the first gate electrode layer, and a gate isolation structure disposed between the first gate electrode layer and the second gate electrode layer. The gate isolation structure includes a first surface and a second surface opposite the first surface. At least a portion of the first surface is in contact with the first gate electrode layer. The second surface includes a first material and a second material different from the first material, and at least a portion of the second surface is in contact with the second gate electrode layer.

公开(公告)号：US20240266225A1

公开(公告)日：2024-08-08

申请号：US18105620

申请日：2023-02-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tzu-Ging LIN ,  Chih-Chang HUNG ,  Shun- Hui YANG

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L27/088

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.

公开(公告)号：US12051700B2

公开(公告)日：2024-07-30

申请号：US18068367

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Wan Chen Hsieh ,  Chung-Ting Ko ,  Tai-Chun Huang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/7851

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

公开(公告)号：US12051694B2

公开(公告)日：2024-07-30

申请号：US18168332

申请日：2023-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Woo Noh ,  Jae-Hyeoung Ma ,  Dong-Il Bae

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device may include first channels on a first region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, second channels on a second region of the substrate and spaced apart from each other in the vertical direction, a first gate structure on the first region of the substrate and covering at least a portion of a surface of each of the first channels, and a second gate structure on the second region of the substrate and covering at least a portion of a surface of each of the second channels. The second channels may be disposed at heights substantially the same as those of corresponding ones of the first channels, and a height of a lowermost one of the second channels may be greater than a height of a lowermost one of the first channels.

公开(公告)号：US12051615B2

公开(公告)日：2024-07-30

申请号：US17445400

申请日：2021-08-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Mengzhu Qiao

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/76283 ,  H01L21/823481

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, an isolation trench being formed on the substrate; a silicon-rich isolation layer is formed in the isolation trench, the silicon-rich isolation layer covering an inner surface of the isolation trench; and an isolation oxide layer is formed in the isolation trench. The isolation oxide layer fills up the isolation trench.

公开(公告)号：US12051614B2

公开(公告)日：2024-07-30

申请号：US17340734

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung Han Hsu ,  Kuan-Cheng Wang ,  Han-Ti Hsiaw ,  Shin-Yeu Tsai

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.