公开(公告)号：US20240112950A1

公开(公告)日：2024-04-04

申请号：US17937464

申请日：2022-10-03

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chia Che CHIANG

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/762

CPC分类号： H01L21/76832 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0337 ,  H01L21/76224 ,  H01L21/76834

摘要： The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a semiconductor layer stack on a metal layer, in which the semiconductor layer stack includes a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, and a third nitride layer; forming a mask layer on the semiconductor layer stack, in which the mask layer includes a plurality of hollowed portions; depositing a thin silicon layer on inner walls of the hollowed portions; and forming a plurality of trenches in the semiconductor layer stack by the hollowed portions.

公开(公告)号：USRE49869E1

公开(公告)日：2024-03-12

申请号：US17214607

申请日：2021-03-26

申请人： iBeam Materials, Inc.

发明人： Vladimir Matias ,  Christopher Yung

IPC分类号： H01L33/32 ,  H01L21/02 ,  H01L31/00 ,  H01L31/036 ,  H01L33/00 ,  H01L33/18 ,  H01L33/64 ,  H01L33/12 ,  H01L33/60

CPC分类号： H01L33/32 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/0262 ,  H01L31/00 ,  H01L31/036 ,  H01L33/007 ,  H01L33/18 ,  H01L33/644 ,  H01L33/12 ,  H01L33/60

摘要： A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used. The user is able to choose a substrate for its mechanical and thermal properties, such as how well its coefficient of thermal expansion matches that of the hexagonal epitaxial layer, while choosing a textured layer that more closely lattice matches that layer. Electronic devices such as LEDs can be manufactured from such structures. Because the substrate can act as both a reflector and a heat sink, transfer to other substrates, and use of external reflectors and heat sinks, is not required, greatly reducing costs. Large area devices such as light emitting strips or sheets may be fabricated using this technology.

公开(公告)号：US20240079486A1

公开(公告)日：2024-03-07

申请号：US18126630

申请日：2023-03-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wei-Ting CHANG ,  Ching Yu CHEN ,  Jiang-He XIE

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/207

CPC分类号： H01L29/7786 ,  H01L21/02104 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/0684 ,  H01L29/2003 ,  H01L29/66462 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L29/207

摘要： A semiconductor structure includes a barrier layer over a channel layer, and a doped layer over the barrier layer. A gate electrode is over the doped layer and a doped interface layer is formed between the barrier layer and the doped layer. The doped interface layer includes a dopant and a metal. The metal has a metal concentration that follows a gradient function from a highest metal concentration to a lowest metal concentration.

公开(公告)号：US20240071761A1

公开(公告)日：2024-02-29

申请号：US18356211

申请日：2023-07-20

申请人： ENKRIS SEMICONDUCTOR, INC.

发明人： Kai Cheng

IPC分类号： H01L21/02 ,  C30B25/04 ,  C30B29/68

CPC分类号： H01L21/02639 ,  C30B25/04 ,  C30B29/68 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458

摘要： In the present disclosure, a semiconductor structure and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes a base, a first mask layer, a first epitaxial layer, and a second epitaxial layer. The first mask layer is located on the base, and the first mask layer has a first window that exposes the base. The first window includes an opening end far from the base and a bottom wall end close to the base. On the plane where the base is located, the orthographic projection of the opening end falls within the bottom wall end.

公开(公告)号：US11901241B2

公开(公告)日：2024-02-13

申请号：US17750579

申请日：2022-05-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Liang Cheng ,  Ziwei Fang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28

CPC分类号： H01L21/823828 ,  H01L21/0228 ,  H01L21/02172 ,  H01L21/02183 ,  H01L21/02458 ,  H01L21/28008 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

摘要： A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

公开(公告)号：US20240047201A1

公开(公告)日：2024-02-08

申请号：US18258784

申请日：2021-12-22

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

发明人： Guy FEUILLET ,  Thierry BOUCHET ,  Matthew CHARLES ,  Roy DAGHER ,  Jesus ZUNIGA PEREZ

IPC分类号： H01L21/02 ,  H01L21/78 ,  H01L29/78 ,  H01L29/66 ,  H01L29/872 ,  H01L29/868 ,  H01L21/8252 ,  H01L27/08 ,  H01L27/085

CPC分类号： H01L21/02505 ,  H01L21/7806 ,  H01L29/7827 ,  H01L29/66212 ,  H01L29/872 ,  H01L29/868 ,  H01L29/66522 ,  H01L29/66204 ,  H01L21/0254 ,  H01L21/0245 ,  H01L21/02447 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02458 ,  H01L21/02381 ,  H01L21/8252 ,  H01L27/0814 ,  H01L27/085

摘要： A method for producing a vertical component comprising with the basis of a III-N material, comprising providing platelets made of the III-N material obtained by epitaxy on pads, the platelets comprise at least first and second layers doped and stacked on one another in a vertical direction. The method further includes the production of a first electrode and the production of a second electrode located on the platelet and configured such that a current passing from one electrode to the other passes through at least the second layer in all of its thickness, the thickness being taken in the vertical direction.

公开(公告)号：US11888083B2

公开(公告)日：2024-01-30

申请号：US17811761

申请日：2022-07-11

申请人： OSRAM Opto Semiconductors GmbH

发明人： Werner Bergbauer ,  Thomas Lehnhardt ,  Jürgen Off ,  Joachim Hertkorn

IPC分类号： H01L31/18 ,  H01L33/12 ,  H01L33/22 ,  H01L21/02 ,  H01L33/00 ,  H01L31/0304 ,  H01L33/32

CPC分类号： H01L31/1852 ,  H01L21/0243 ,  H01L21/0254 ,  H01L21/02458 ,  H01L21/02639 ,  H01L21/02647 ,  H01L31/03044 ,  H01L31/1856 ,  H01L33/007 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/22 ,  H01L33/32 ,  H01L21/02488 ,  H01L2933/0033

摘要： In an embodiment an electronic semiconductor chip includes a growth substrate with a growth surface including a flat region having a plurality of three-dimensionally designed surface structures on the flat region, a nucleation layer composed of oxygen-containing AlN in direct contact with the growth surface at the flat region and the three-dimensionally designed surface structures and a nitride-based semiconductor layer sequence on the nucleation layer, wherein the semiconductor layer sequence overlays the three-dimensionally designed surface structures, and wherein the oxygen content in the nucleation layer is greater than 1019 cm−3.

公开(公告)号：US11869942B2

公开(公告)日：2024-01-09

申请号：US16643003

申请日：2018-08-16

申请人： SILTRONIC AG

发明人： Sarad Bahadur Thapa ,  Martin Vorderwestner

IPC分类号： H01L29/15 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC分类号： H01L29/155 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

摘要： A heteroepitaxial wafer comprises, in the following order: a silicon substrate having a diameter and a thickness;



an AlN nucleation layer;
a first strain building layer which is an AlzGal-zN layer having a first average Al content z, wherein 0

公开(公告)号：US11855199B2

公开(公告)日：2023-12-26

申请号：US17083715

申请日：2020-10-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ling Yeh ,  Pravanshu Mohanta ,  Ching-Yu Chen ,  Jiang-He Xie ,  Yu-Shine Lin

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC分类号： H01L29/7786 ,  H01L21/0254 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/30612 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

摘要： Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).

公开(公告)号：US20230343588A1

公开(公告)日：2023-10-26

申请号：US18297657

申请日：2023-04-10

申请人： GlobalWafers Co., Ltd.

发明人： Po Jung Lin ,  Jia-Zhe Liu

IPC分类号： H01L21/02

CPC分类号： H01L21/02458 ,  H01L21/02378 ,  H01L21/0254

摘要： A semiconductor structure includes a silicon carbide (SiC) substrate, a nucleation layer and a gallium nitride (GaN) layer. The silicon carbide layer has a first thickness T1. The nucleation layer is located on the silicon carbide layer and has a second thickness T2. The nucleation layer is made of AlGaN (AlGaN), and the second thickness T2 fulfills a thickness range of T1*0.002% to T1*0.006%. The gallium nitride layer is located on the nucleation layer and is separated from the silicon carbide substrate.