知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

860 records (took 0.029 seconds)

    Semiconductor memory device
    21.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US09548107B1

    公开(公告)日：2017-01-17

    申请号：US14963482

    申请日：2015-12-09

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Naoko Kifune ,  Masanobu Shirakawa ,  Ryo Yamaki ,  Osamu Torii

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56

    CPC classification number: G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/5642 ,  G11C2211/5648

    Abstract: A semiconductor memory device includes a memory cell configured to hold 4-bit data according to a threshold. A first bit of the 4-bit data is established by reading operations using a first to a third read levels. A second bit different from the first bit is established by reading operations using a fourth to a seventh read levels. A third bit different from the first and second bits is established by reading operations using an eighth to an eleventh read levels. A fourth bit different from the first to third bits is established by reading operations using a twelfth to a fifteenth read levels.

    Abstract translation: 半导体存储器件包括被配置为根据阈值保持4位数据的存储器单元。 通过使用第一至第三读取电平读取操作来建立4位数据的第一位。 通过使用第四到第七读取电平的读取操作来建立与第一位不同的第二位。 通过使用第八到第十一读取电平的读取操作来建立与第一和第二位不同的第三位。 通过使用第十二至第十五读取电平的读取操作来建立与第一至第三位不同的第四位。

    Two-part programming methods
    23.
    发明授权
    Two-part programming methods 有权
    两部分编程方法

    公开(公告)号：US09502101B2

    公开(公告)日：2016-11-22

    申请号：US14725749

    申请日：2015-05-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C11/5628 ,  G11C16/0408 ,  G11C16/0458 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/562 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5648

    Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programming the first memory cell to the first level. After programming the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programming the second memory cell to the second level.

    Abstract translation: 使用第一编程电压范围内的第一组编程脉冲将第一存储单元编程为第一电平。 在将第一存储器单元编程到第一电平时，禁止要编程到小于第一电平的第二电平的第二存储器单元。 在将第一存储器单元编程到第一电平之后，使用第二编程电压范围内的第二组编程脉冲将第二存储单元编程为第二电平，其中第一编程电压范围与第二编程电压范围重叠。 在将第二存储器单元编程到第二级时，禁止编程到第一级的第一存储单元。

    DATA PROCESSING SYSTEM HAVING COMBINED MEMORY BLOCK AND STACK PACKAGE
    24.
    发明申请
    DATA PROCESSING SYSTEM HAVING COMBINED MEMORY BLOCK AND STACK PACKAGE 审中-公开
    具有组合记忆块和堆叠包的数据处理系统

    公开(公告)号：US20160210235A1

    公开(公告)日：2016-07-21

    申请号：US15063012

    申请日：2016-03-07

    Applicant: SK hynix Inc.

    Inventor： Hae Chan PARK ,  Sung Cheoul KIM ,  Tae Ho KIM

    IPC: G06F12/08 ,  G06F13/40

    CPC classification number: G06F13/4022 ,  G06F2212/451 ,  G11C11/005 ,  G11C11/5607 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/06 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2213/71 ,  G11C2213/79 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.

    Abstract translation: 数据处理系统包括中央处理单元（CPU），配置成与CPU接口的控制块，配置为与控制块接口并被布置为与CPU间隔第一距离的高速缓存存储器，以及组合存储器 其被配置为与所述控制块接口，被布置成与所述CPU间隔大于所述第一距离的第二距离，并且由工作存储器和存储存储器构成。 组合存储块由多个堆叠存储器层构成，每个堆叠存储层由多个可变电阻存储单元构成。 工作存储器被分配给在多个存储器层中选择的一个存储器层。 存储存储器被分配给多个存储器层中的剩余存储器层。

    Programming management data for a memory
    26.
    发明授权
    Programming management data for a memory 有权
    为存储器编程管理数据

    公开(公告)号：US08943387B2

    公开(公告)日：2015-01-27

    申请号：US13904331

    申请日：2013-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Michael Murray ,  William Henry Radke

    IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

    CPC classification number: G06F11/1008 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C2211/5642

    Abstract: Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Additional embodiments may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additional embodiments may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.

    Abstract translation: 方法，装置，系统和数据结构可以操作以将块管理数据与数据的一部分组合，以产生组合部分的纠错数据，并存储数据，块管理数据，组合的纠错数据 部分和用于存储器中的数据的纠错数据。 另外的实施例可以操作以生成或存储除了页面中的特定扇区之外的页面的多个扇区中的每一个的纠错数据，并且将块管理数据与特定扇区组合以生成修改的扇区。 另外的实施例可以操作以产生或存储修改的扇区的纠错数据，并组合多个扇区，除了特定页面之外的多个扇区中的每一个的纠错数据以及块管理数据和用于 修改部门。

    DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF
    27.
    发明申请
    DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
    具有多位存储器件的数据存储系统及其操作方法

    公开(公告)号：US20140313824A1

    公开(公告)日：2014-10-23

    申请号：US14319137

    申请日：2014-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangyong Yoon ,  Kitae Park ,  Jinman Han ,  Wonseok Lee

    IPC: G11C16/10 ,  G11C14/00

    CPC classification number: G11C16/10 ,  G11C11/56 ,  G11C11/5628 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

    Abstract: A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory. The operating method of the data storage device includes storing data in the buffer memory, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the program pattern.

    Abstract translation: 数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器的存储器控​​制器。 数据存储装置的操作方法包括将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是伴随存储器单元阵列的缓冲器程序操作的数据。 当存储在缓冲存储器中的数据是伴随缓冲器程序操作的数据时，该方法还包括确定是否需要对存储单元阵列执行主程序操作，并且当需要存储单元阵列的主程序操作时， 存储单元阵列中的主程序操作的程序模式。 该方法还包括基于该程序模式向存储单元阵列发出用于主程序操作的一组命令到多位存储器件。

    Semiconductor memory device which stores multilevel data
    28.
    发明授权
    Semiconductor memory device which stores multilevel data 有权
    存储多级数据的半导体存储器件

    公开(公告)号：US08837213B2

    公开(公告)日：2014-09-16

    申请号：US13836914

    申请日：2013-03-15

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Noboru Shibata

    IPC: G11C16/04 ,  G11C16/12 ,  G11C16/26 ,  G11C11/56

    CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5646 ,  G11C2216/14

    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a flag memory cell for a flag, a dummy cell and a controller. The flag memory cell is selected at the same time as the memory cell. The dummy cell is selected at the same time as the memory cell and the flag memory cell. The controller controls write and read of the memory cell, the flag memory cell and the dummy cell. Data is written also in the dummy cell which neighbors the flag cell.

    Abstract translation: 根据一个实施例，半导体存储器件包括存储器单元，用于标志的标志存储单元，虚设单元和控制器。 与存储单元同时选择标志存储单元。 与存储单元和标志存储单元同时选择虚拟单元。 控制器控制存储单元，标志存储单元和虚拟单元的写和读。 数据也写入邻近标志单元的虚拟单元中。

    Clock synchronized non-volatile memory device
    29.
    发明授权
    Clock synchronized non-volatile memory device 有权
    时钟同步非易失性存储器件

    公开(公告)号：US08804431B2

    公开(公告)日：2014-08-12

    申请号：US13453079

    申请日：2012-04-23

    Applicant: Hitoshi Miwa ,  Hiroaki Kotani

    Inventor： Hitoshi Miwa ,  Hiroaki Kotani

    IPC: G11C11/34

    CPC classification number: G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    Abstract: A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

    Abstract translation: 一种非易失性存储装置，包括控制电路，具有时钟，命令和其他端子的多个端子，数据和命令寄存器以及多个非易失性存储单元。 时钟终端接收时钟信号，命令终端接收包括读取和编程命令的命令。 数据寄存器从外部接收数据并输出数据。 控制电路从用于控制设备的存储器读取操作步骤。 控制电路响应于读取命令控制从存储器单元读取数据，将读取的数据存储到数据寄存器，并且经由另一终端而不是命令终端基于时钟信号输出读取数据。 控制电路响应于程序命令，控制基于时钟信号经由另一终端而不是命令终端接收数据，将接收的数据存储到数据寄存器，并将接收的数据写入存储单元。

Patent Agency Ranking