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    Nonvolatile memory system, semiconductor memory and writing method
    1.
    发明授权
    Nonvolatile memory system, semiconductor memory and writing method 有权
    非易失性存储器系统，半导体存储器和写入方法

    公开(公告)号：US08004905B2

    公开(公告)日：2011-08-23

    申请号：US12726485

    申请日：2010-03-18

    申请人： Tatsuya Ishii ,  Hitoshi Miwa ,  Osamu Tsuchiya ,  Shooji Kubono

    发明人： Tatsuya Ishii ,  Hitoshi Miwa ,  Osamu Tsuchiya ,  Shooji Kubono

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3427 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3431 ,  G11C16/3459 ,  G11C2216/18

    摘要： A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

    摘要翻译： 非易失性半导体存储器由于与字线相关的干扰而恢复存储器单元的阈值的变化。 非易失性存储器在每次写入操作之后连续执行许多写入操作，而不执行单扇区擦除，执行比通常的写入操作更快的附加写入操作，以及减轻用于附加写入的软件的负担。 存储在指定扇区中的数据在保存在寄存器中之前被读出，并且当给出预定命令时，所选扇区被进行单扇区擦除。 然后写入预期值数据由保存的数据和要另外编写的数据形成，完成写入操作。

    CLOCK SYNCHRONIZED NON-VOLATILE MEMORY DEVICE
    2.
    发明申请
    CLOCK SYNCHRONIZED NON-VOLATILE MEMORY DEVICE 审中-公开
    时钟同步非易失性存储器件

    公开(公告)号：US20100020615A1

    公开(公告)日：2010-01-28

    申请号：US12434794

    申请日：2009-05-04

    申请人： Hitoshi MIWA ,  Hiroaki Kotani

    发明人： Hitoshi MIWA ,  Hiroaki Kotani

    IPC分类号： G11C16/04 ,  G11C8/18

    CPC分类号： G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    摘要： A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

    摘要翻译： 一种非易失性存储装置，包括控制电路，具有时钟，命令和其他端子的多个端子，数据和命令寄存器以及多个非易失性存储单元。 时钟终端接收时钟信号，命令终端接收包括读取和编程命令的命令。 数据寄存器从外部接收数据并输出数据。 控制电路从用于控制设备的存储器读取操作步骤。 控制电路响应于读取命令控制从存储器单元读取数据，将读取的数据存储到数据寄存器，并且经由另一终端而不是命令终端基于时钟信号输出读取数据。 控制电路响应于程序命令，控制基于时钟信号经由另一终端而不是命令终端接收数据，将接收的数据存储到数据寄存器，并将接收的数据写入存储单元。

    Clock synchronized nonvolatile memory device
    3.
    发明授权
    Clock synchronized nonvolatile memory device 有权
    时钟同步非易失性存储器件

    公开(公告)号：US07286397B2

    公开(公告)日：2007-10-23

    申请号：US11088945

    申请日：2005-03-25

    申请人： Hitoshi Miwa ,  Hiroaki Kotani

    发明人： Hitoshi Miwa ,  Hiroaki Kotani

    IPC分类号： G11C11/34

    CPC分类号： G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    摘要： A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

    摘要翻译： 一种非易失性存储装置，包括控制电路，具有时钟，命令和其他端子的多个端子，数据和命令寄存器以及多个非易失性存储单元。 时钟终端接收时钟信号，命令终端接收包括读取和编程命令的命令。 数据寄存器从外部接收数据并输出数据。 控制电路从用于控制设备的存储器读取操作步骤。 控制电路响应于读取命令控制从存储器单元读取数据，将读取的数据存储到数据寄存器，并且经由另一终端而不是命令终端基于时钟信号输出读取数据。 控制电路响应于程序命令，控制基于时钟信号经由另一终端而不是命令终端接收数据，将接收的数据存储到数据寄存器，并将接收的数据写入存储单元。

    Clock synchronized non-volatile memory device
    4.
    发明申请
    Clock synchronized non-volatile memory device 有权
    时钟同步非易失性存储器件

    公开(公告)号：US20070064483A1

    公开(公告)日：2007-03-22

    申请号：US11600798

    申请日：2006-11-17

    申请人： Hitoshi Miwa ,  Hiroaki Kotani

    发明人： Hitoshi Miwa ,  Hiroaki Kotani

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    摘要： A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

    摘要翻译： 一种非易失性存储装置，包括控制电路，具有时钟，命令和其他端子的多个端子，数据和命令寄存器以及多个非易失性存储单元。 时钟终端接收时钟信号，命令终端接收包括读取和编程命令的命令。 数据寄存器从外部接收数据并输出数据。 控制电路从用于控制设备的存储器读取操作步骤。 控制电路响应于读取命令控制从存储器单元读取数据，将读取的数据存储到数据寄存器，并且经由另一终端而不是命令终端基于时钟信号输出读取数据。 控制电路响应于程序命令，控制基于时钟信号经由另一终端而不是命令终端接收数据，将接收的数据存储到数据寄存器，并将接收的数据写入存储单元。

    Clock synchronized non-volatile memory device
    6.
    发明授权
    Clock synchronized non-volatile memory device 失效
    时钟同步非易失性存储器件

    公开(公告)号：US06898118B2

    公开(公告)日：2005-05-24

    申请号：US10373707

    申请日：2003-02-27

    申请人： Hitoshi Miwa ,  Hiroaki Kotani

    发明人： Hitoshi Miwa ,  Hiroaki Kotani

    IPC分类号： G11C11/56 ,  G11C11/34

    CPC分类号： G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    摘要： A nonvolatile memory apparatus which includes a control circuit, plural terminals including a clock, command and other terminals, a converter circuit, and plural of nonvolatile memory cells. The clock terminal receives a clock signal, the command terminal receives commands including a read and program commands, and the control circuit reads out operation steps from a program memory to be executed to control an operation of the received command. In an operation in response to the read command, the control circuit controls reading data in parallel from ones of the nonvolatile memory cells, converting parallel type data to serial type data by the converter circuit, and serially outputting data via the other terminal except the command terminal in response to the clock signal. In an operation in response to the program, the control circuit controls serially receiving data via the other terminal except the command terminal in response to the clock signal, converting serial type data to parallel type data by the converter circuit, and writing data in parallel to ones of the nonvolatile memory cells.

    摘要翻译： 一种非易失性存储装置，包括控制电路，包括时钟，命令和其他端子的多个端子，转换器电路和多个非易失性存储单元。 时钟端子接收时钟信号，命令终端接收包括读取和编程命令的命令，并且控制电路从要执行的程序存储器中读出操作步骤以控制接收到的命令的操作。 在响应于读取命令的操作中，控制电路从非易失性存储单元中并行地控制读取数据，通过转换器电路将并行类型数据转换为串行数据，并且除了命令之外经由另一个终端串行输出数据 终端响应时钟信号。 在响应于程序的操作中，控制电路响应于时钟信号，经由除了命令终端之外的另一终端串行地接收数据，通过转换器电路将串行类型数据转换为并行类型数据，并且并行地写入数据 非易失性存储单元。

    Clock synchronized nonvolatile memory device
    7.
    发明授权
    Clock synchronized nonvolatile memory device 失效
    时钟同步非易失性存储器件

    公开(公告)号：US06850434B2

    公开(公告)日：2005-02-01

    申请号：US10810626

    申请日：2004-03-29

    申请人： Hitoshi Miwa ,  Hiroaki Kotani

    发明人： Hitoshi Miwa ,  Hiroaki Kotani

    IPC分类号： G11C11/56 ,  G11C11/34

    CPC分类号： G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    摘要： A nonvolatile memory apparatus including plural terminals having clock, command and other terminals, a clock generator, and plural nonvolatile memory cells. The clock and command terminals respectively receive a first clock signal and commands having read and program commands. The clock generator generates a second clock signal. In response to the read command, the apparatus reads data from the memory cells, and outputs data to outside of the apparatus in response to the first clock signal via the other terminal except the command terminal. In response to the program command, the apparatus receives data from outside of the apparatus in response to the first clock signal via the other terminal except the command terminal and writes data to the memory cells. The data writing to the memory cells is performed using the second clock signal.

    摘要翻译： 一种非易失性存储装置，包括具有时钟，命令和其他终端的多个终端，时钟发生器和多个非易失性存储单元。 时钟和命令终端分别接收第一时钟信号和具有读取和编程命令的命令。 时钟发生器产生第二个时钟信号。 响应于该读取命令，该设备从存储器单元读取数据，并且响应于除了命令终端之外的另一个终端的第一时钟信号将数据输出到设备外部。 响应于该程序命令，该装置响应于第一时钟信号经由除命令终端之外的另一终端从设备外部接收数据，并将数据写入存储单元。 使用第二时钟信号执行对存储器单元的写入。

    Clock synchronized non-volatile memory device
    8.
    发明授权
    Clock synchronized non-volatile memory device 失效
    时钟同步非易失性存储器件

    公开(公告)号：US06801452B2

    公开(公告)日：2004-10-05

    申请号：US10223220

    申请日：2002-08-20

    申请人： Hitoshi Miwa ,  Hiroaki Kotani

    发明人： Hitoshi Miwa ,  Hiroaki Kotani

    IPC分类号： G11C1134

    CPC分类号： G11C16/32 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5647 ,  G11C2211/565

    摘要： A nonvolatile memory apparatus including plural terminals having clock, command and other terminals, plural nonvolatile memory cells, and first and second volatile memories. The clock and command terminals receive respectively a first clock signal and commands including read and program commands. In response to the read command, the apparatus reads data from the memory cells, stores read data to the second volatile memory, transfers the data to the first volatile memory, and outputs the data to outside via the other terminal not the command terminal based on the first clock signal. In response to the program command, the apparatus receives data from outside via the other terminal not the command terminal based on the first clock signal, stores the received data to the first volatile memory, transfers the data to the second volatile memory, and writes the data from the second volatile memory to the memory cells.

    摘要翻译： 一种非易失性存储装置，包括具有时钟，命令和其他终端的多个终端，多个非易失性存储单元以及第一和第二易失性存储器。 时钟和命令终端分别接收第一时钟信号和包括读取和编程命令的命令。 响应于读取命令，设备从存储器单元读取数据，将读取的数据存储到第二易失性存储器，将数据传送到第一易失性存储器，并且经由另一终端而不是命令终端将数据输出到外部 第一个时钟信号。 响应于程序命令，该装置基于第一时钟信号经由另一终端而不是命令终端从外部接收数据，将接收的数据存储到第一易失性存储器，将数据传送到第二易失性存储器，并将该数据写入 从第二易失性存储器到存储器单元的数据。