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    MULTI-LEVEL STARVATION WIDGET
    22.
    发明公开
    MULTI-LEVEL STARVATION WIDGET 审中-公开

    公开(公告)号：US20240111684A1

    公开(公告)日：2024-04-04

    申请号：US17957479

    申请日：2022-09-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sankaranarayanan Gurumurthy ,  Anil Harwani

    IPC: G06F12/0897

    CPC classification number: G06F12/0897 ,  G06F2212/601

    Abstract: The disclosed method includes detecting a stalled memory request, for a first level cache within a cache hierarchy of a processor, that includes an outstanding memory request associated with a second level cache within the cache hierarchy that is higher than the first level cache. The method further includes indicating, to the second level cache, that the first level cache is experiencing a starvation issue due to stalled memory requests to enable the second level cache to perform starvation-remediation actions. Various other methods, systems, and computer-readable media are also disclosed.

    Method and apparatus for data-ready memory operations
    23.
    发明授权
    Method and apparatus for data-ready memory operations 有权

    公开(公告)号：US11934830B2

    公开(公告)日：2024-03-19

    申请号：US17839071

    申请日：2022-06-13

    Applicant: Intel Corporation

    Inventor： William M. Brown ,  Mikhail Plotnikov ,  Christopher J. Hughes

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0897

    CPC classification number: G06F9/30047 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/3016 ,  G06F9/3824 ,  G06F9/3836 ,  G06F12/0897

    Abstract: Disclosed embodiments relate to a new instruction for performing data-ready memory access operations. In one example, a system includes circuits to fetch, decode, and execute an instruction that includes an opcode, at least one memory location identifier identifying at least one data element, a register identifier, a data readiness indicator identifying at least one data access condition, and a data readiness mask, wherein the execution circuit is to, for each data element of the at least one data element, determine whether a memory request for the data element satisfies the at least one data access condition identified by the data readiness indicator, and in response to determining that the memory request for the data element does not satisfy the at least one data access condition: generate a prefetch request for the data element, and set a value in a corresponding data element position of the data readiness mask to indicate that the memory request for the data element does not satisfy the at least one data access condition.

    Memory-aware pre-fetching and cache bypassing systems and methods
    24.
    发明授权
    Memory-aware pre-fetching and cache bypassing systems and methods 有权

    公开(公告)号：US11934317B2

    公开(公告)日：2024-03-19

    申请号：US17543378

    申请日：2021-12-06

    Applicant: Lodestar Licensing Group, LLC

    Inventor： David Andrew Roberts

    IPC: G06F12/0888 ,  G06F12/0862 ,  G06F12/0897

    CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F12/0897

    Abstract: Systems, apparatuses, and methods for memory management are described. For example, these may include a first memory level including memory pages in a memory array, a second memory level including a cache, a pre-fetch buffer, or both, and a memory controller that determines state information associated with a memory page in the memory array targeted by a memory access request. The state information may include a first parameter indicative of a current activation state of the memory page and a second parameter indicative of statistical likelihood (e.g., confidence) that a subsequent memory access request will target the memory page. The memory controller may disable storage of data associated with the memory page in the second memory level when the first parameter associated with the memory page indicates that the memory page is activated and the second parameter associated with the memory page is greater than or equal to a threshold.

    Load-Store Pipeline Selection For Vectors
    29.
    发明公开
    Load-Store Pipeline Selection For Vectors 审中-公开

    公开(公告)号：US20230367715A1

    公开(公告)日：2023-11-16

    申请号：US18141463

    申请日：2023-04-30

    Applicant: SiFive, Inc.

    Inventor： Andrew Waterman ,  Krste Asanovic

    IPC: G06F12/0855 ,  G06F12/0897 ,  G06F12/0815 ,  G06F12/0875

    CPC classification number: G06F12/0855 ,  G06F12/0897 ,  G06F12/0815 ,  G06F12/0875

    Abstract: Systems and methods are disclosed for load-store pipeline selection for vectors. For example, an integrated circuit (e.g., a processor) for executing instructions includes an L1 cache that provides an interface to a memory system; an L2 cache connected to the L1 cache that implements a cache coherency protocol with the L1 cache; a first store unit configured to write data to the memory system via the L1 cache; a second store unit configured to bypass the L1 cache and write data to the memory system via the L2 cache; and a store pipeline selection circuitry configured to: identify an address associated with a first beat of a store instruction with a vector argument; select between the first store unit and the second store unit based on the address associated with the first beat of the store instruction; and dispatch the store instruction to the selected store unit.

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