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公开(公告)号：US11792998B1
公开(公告)日：2023-10-17
申请号：US17346090
申请日：2021-06-11
发明人： Noriyuki Sato , Tanay Gosavi , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Sasikanth Manipatruni
IPC分类号： H10B53/40
CPC分类号： H10B53/40
摘要： A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.
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22.发明授权公开(公告)号：US11792997B1
公开(公告)日：2023-10-17
申请号：US17517945
申请日：2021-11-03
IPC分类号： G11C11/00 , H10B53/30 , G11C11/22 , H01L25/065 , H10B53/40
CPC分类号： H10B53/30 , G11C11/2255 , G11C11/2257 , H01L25/0655 , H10B53/40
摘要： To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
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23.发明授权公开(公告)号：US11790969B1
公开(公告)日：2023-10-17
申请号：US17344815
申请日：2021-06-10
CPC分类号： G11C11/221 , G06F12/0246 , G11C11/02 , G11C11/225 , G11C13/0002 , G11C13/0035 , G06F2212/7202 , G06F2212/7211
摘要： Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.
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公开(公告)号：US11784164B2
公开(公告)日：2023-10-10
申请号：US17472308
申请日：2021-09-10
IPC分类号： H01L25/065 , H01L23/31 , H01L23/498 , H01L23/538 , H01L23/48 , H01L23/367 , H01L23/00 , H01L25/18 , H01L25/00 , H10B41/42
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/3672 , H01L23/481 , H01L23/49811 , H01L23/49894 , H01L23/5389 , H01L24/17 , H01L25/18 , H01L25/50 , H10B41/42 , H01L2924/1431 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1441 , H01L2924/14335
摘要： Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.
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公开(公告)号：US20230308102A1
公开(公告)日：2023-09-28
申请号：US18320163
申请日：2023-05-18
发明人： Sasikanth Manipatruni , Yuan-Sheng Fang , Robert Menezes , Rajeev Kumar Dokania , Guarav Thareja , Ramamoorthy Ramesh , Amrita Mathuriya
摘要： An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.
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公开(公告)号：US11765909B1
公开(公告)日：2023-09-19
申请号：US17345964
申请日：2021-06-11
发明人： Noriyuki Sato , Tanay Gosavi , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Sasikanth Manipatruni
IPC分类号： H10B53/40
CPC分类号： H10B53/40
摘要： A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.
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公开(公告)号：US11758708B1
公开(公告)日：2023-09-12
申请号：US17517345
申请日：2021-11-02
CPC分类号： H10B12/30 , G11C5/10 , G11C11/221 , G11C11/4023 , H10B53/20
摘要： To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
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公开(公告)号：US11744081B1
公开(公告)日：2023-08-29
申请号：US17315139
申请日：2021-05-07
发明人： Niloy Mukherjee , Ramamoorthy Ramesh , Sasikanth Manipatruni , James Clarkson , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Jason Y. Wu
摘要： Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.
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公开(公告)号：US11737283B1
公开(公告)日：2023-08-22
申请号：US17516594
申请日：2021-11-01
摘要： To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
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30.发明授权公开(公告)号：US11716084B1
公开(公告)日：2023-08-01
申请号：US17645872
申请日：2021-12-23
发明人： Sasikanth Manipatruni , Nabil Imam , Ikenna Odinaka , Rafael Rios , Rajeev Kumar Dokania , Amrita Mathuriya
CPC分类号： H03K19/23 , H03K19/0813
摘要： Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.
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