公开(公告)号：US20120098871A1

公开(公告)日：2012-04-26

申请号：US13167155

申请日：2011-06-23

Applicant: Tae-Hyeong PARK ,  Dong-Ho LEE ,  Joon-Ha PARK ,  Sang-Cheol SHIN

Inventor： Tae-Hyeong PARK ,  Dong-Ho LEE ,  Joon-Ha PARK ,  Sang-Cheol SHIN

IPC: G09G5/10 ,  H01L33/08

CPC classification number: G09G3/2003 ,  G09G3/36 ,  G09G3/3607 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0297 ,  G09G2320/0242 ,  G09G2320/0247 ,  G09G2320/0276 ,  G09G2340/06

Abstract: A display panel includes a plurality of pixels including at least four even-numbered subpixels. The at least four even-numbered subpixels includes: a first red subpixel including a pixel electrode electrically connected to a switching element which is connected to a first data line and a first gate line; a first green subpixel including a pixel electrode electrically connected to a switching element which is connected to a second data line and a second gate line, where the second data line is disposed adjacent to the first data line; a first blue subpixel including a pixel electrode electrically connected to a switching element which is connected to the first data line and the second gate line; and a first multi-primary subpixel including a pixel electrode electrically connected to a switching element which is connected to the second data line and the first gate line.

Abstract translation: 显示面板包括包括至少四个偶数子像素的多个像素。 所述至少四个偶数子像素包括：第一红色子像素，包括电连接到与第一数据线和第一栅极线连接的开关元件的像素电极; 第一绿色子像素，包括电连接到与第二数据线连接的开关元件的像素电极和第二栅极线，其中第二数据线被布置为与第一数据线相邻; 第一蓝色子像素，包括电连接到与第一数据线和第二栅极线连接的开关元件的像素电极; 以及包括与连接到第二数据线和第一栅极线的开关元件电连接的像素电极的第一多原子像素。

公开(公告)号：US20090079496A1

公开(公告)日：2009-03-26

申请号：US12238894

申请日：2008-09-26

Applicant: Byung-Se SO ,  Dong-Ho LEE ,  Hyun-Soon JANG

Inventor： Byung-Se SO ,  Dong-Ho LEE ,  Hyun-Soon JANG

IPC: H01L25/00 ,  H05K7/00

CPC classification number: H01L24/49 ,  G11C5/00 ,  G11C5/06 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

Abstract translation: 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。 第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。 此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。

公开(公告)号：US20090065950A1

公开(公告)日：2009-03-12

申请号：US12267343

申请日：2008-11-07

Applicant: Jong-Joo LEE ,  Dong-Ho LEE

Inventor： Jong-Joo LEE ,  Dong-Ho LEE

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

Abstract translation: 提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。 两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。 半导体芯片具有芯片焊盘，输入/输出缓冲器和通过电路布线连接的内部电路。 半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。 半导体芯片包括第一芯片和第二芯片。 第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。 通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。

公开(公告)号：US20090036328A1

公开(公告)日：2009-02-05

申请号：US12179219

申请日：2008-07-24

Applicant: June-Young LEE ,  Dong-Ho LEE

Inventor： June-Young LEE ,  Dong-Ho LEE

IPC: C40B60/12

CPC classification number: C40B60/12 ,  B01L3/508 ,  B01L2200/16 ,  B01L2300/047 ,  B01L2300/0636

Abstract: A biochip package allowing biochips optimized for high-volume production to be compatible with general-purpose devices and a biochip packaging substrate of the biochip package are provided. The biochip package can include a biochip having a probe array mounted thereon and a biochip packaging substrate on which the biochip is mounted and which has a through cavity exposing a rear surface of the biochip.

Abstract translation: 提供了一种生物芯片封装，允许针对大批量生产优化的生物芯片与通用器件和生物芯片封装的生物芯片封装衬底兼容。 生物芯片封装可以包括其上安装有探针阵列的生物芯片和其上安装有生物芯片的生物芯片封装衬底，并且具有暴露生物芯片后表面的通孔。

公开(公告)号：US20080159919A1

公开(公告)日：2008-07-03

申请号：US11946770

申请日：2007-11-28

Applicant: June-Young LEE ,  Dong-Ho LEE

Inventor： June-Young LEE ,  Dong-Ho LEE

IPC: B01L11/00 ,  G01N33/566

CPC classification number: B01L3/508 ,  B01L1/52 ,  B01L2200/026 ,  B01L2300/045 ,  B01L2300/0636 ,  B01L2300/0809

Abstract: Provided is a biochip kit and a method capable of detecting the binding of target molecules in a biological sample to at least one probe on a biochip. The biochip kit includes a housing, a biochip, disposed in the housing, including at least one probe, and a lid, connectedly installed on the housing, such that the lid can open or close the housing.

Abstract translation: 提供了一种生物芯片试剂盒和能够检测生物样品中的靶分子与生物芯片上的至少一种探针的结合的方法。 生物芯片套件包括壳体，生物芯片，设置在壳体中，包括至少一个探针和连接安装在壳体上的盖，使得盖可以打开或关闭壳体。

公开(公告)号：US20080014735A1

公开(公告)日：2008-01-17

申请号：US11775120

申请日：2007-07-09

Applicant: Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

Inventor： Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

Abstract translation: 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。

公开(公告)号：US20070132108A1

公开(公告)日：2007-06-14

申请号：US11677478

申请日：2007-02-21

Applicant: Jin-Hyuk LEE ,  Gu-Sung KIM ,  Dong-Ho LEE ,  Dong-Hyeon JANG

Inventor： Jin-Hyuk LEE ,  Gu-Sung KIM ,  Dong-Ho LEE ,  Dong-Hyeon JANG

IPC: H01L23/48

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/02 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433

Abstract: A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.

Abstract translation: 提供了具有芯片焊盘和钝化层的半导体芯片的半导体晶片。 第一和第二电介质层依次形成在钝化层上。 第一和第二电介质层形成包括压花部分，即具有非平面表面的球垫区域。 在所得到的包括压纹部分的结构上形成金属布线层。 第三电介质层形成在金属布线层上。 位于压花部分上的第三电介质层的一部分被去除以形成球垫。 在浮雕球垫上形成焊球。 利用压纹球垫，焊球和金属布线层之间的接触面积增加，从而提高连接可靠性。