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    MULTI-BIT FLIP FLOP
    23.
    发明申请
    MULTI-BIT FLIP FLOP 有权

    公开(公告)号：US20210203311A1

    公开(公告)日：2021-07-01

    申请号：US17082368

    申请日：2020-10-28

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chi-Lin Liu ,  Shang-Chih Hsieh ,  Wei-Hsiang Ma

    IPC: H03K3/037 ,  H03K19/21

    Abstract: A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

    MULTIPLEXER
    26.
    发明申请
    MULTIPLEXER 有权

    公开(公告)号：US20240411976A1

    公开(公告)日：2024-12-12

    申请号：US18788458

    申请日：2024-07-30

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chi-Lin Liu ,  Shang-Chih Hsieh ,  Jian-Sing Li ,  Wei-Hsiang Ma ,  Yi-Hsun Chen ,  Cheok-Kei Lei

    IPC: G06F30/392 ,  G06F30/347 ,  G06F30/39 ,  H01L27/02

    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

    Flip-flop with delineated layout for reduced footprint
    28.
    发明授权
    Flip-flop with delineated layout for reduced footprint 有权

    公开(公告)号：US12015409B2

    公开(公告)日：2024-06-18

    申请号：US17339121

    申请日：2021-06-04

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chi-Lin Liu ,  Ting-Wei Chiang ,  Jerry Chang-Jui Kao ,  Hui-Zhong Zhuang ,  Lee-Chung Lu ,  Shang-Chih Hsieh ,  Che Min Huang

    IPC: H03K3/3562 ,  G01R31/3185 ,  H01L27/02 ,  H01L27/092

    CPC classification number: H03K3/35625 ,  G01R31/318541 ,  H01L27/0207 ,  H01L27/092

    Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

    Flip-flop device and method of operating flip-flop device
    30.
    发明授权
    Flip-flop device and method of operating flip-flop device 有权

    公开(公告)号：US11996842B2

    公开(公告)日：2024-05-28

    申请号：US18056262

    申请日：2022-11-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Greg Gruber ,  Chi-Lin Liu ,  Ming-Chang Kuo ,  Lee-Chung Lu ,  Shang-Chih Hsieh

    IPC: H03K19/00 ,  G01R31/3185

    CPC classification number: H03K19/0013 ,  G01R31/318536

    Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

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