公开(公告)号：US11996842B2

公开(公告)日：2024-05-28

申请号：US18056262

申请日：2022-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Greg Gruber ,  Chi-Lin Liu ,  Ming-Chang Kuo ,  Lee-Chung Lu ,  Shang-Chih Hsieh

IPC: H03K19/00 ,  G01R31/3185

CPC classification number: H03K19/0013 ,  G01R31/318536

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

公开(公告)号：US11509306B2

公开(公告)日：2022-11-22

申请号：US17353674

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Greg Gruber ,  Chi-Lin Liu ,  Ming-Chang Kuo ,  Lee-Chung Lu ,  Shang-Chih Hsieh

IPC: H03K19/00 ,  G01R31/3185

Abstract: An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

公开(公告)号：US11050423B1

公开(公告)日：2021-06-29

申请号：US16744836

申请日：2020-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Greg Gruber ,  Chi-Lin Liu ,  Ming-Chang Kuo ,  Lee-Chung Lu ,  Shang-Chih Hsieh

IPC: H03K19/00 ,  G01R31/3185

Abstract: An integrated circuit includes: a flip-flop circuit arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode; and a gating circuit coupled to the flip-flop circuit, for generating the first clock signal and the second clock signal according to the master signal and an input clock signal; wherein a first signal transition number of the first clock signal and a second signal transition number of the second clock signal are not greater than a third signal transition number of the input clock signal during the writing mode and the storing mode.