公开(公告)号：US20210135105A1

公开(公告)日：2021-05-06

申请号：US16939497

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Cheng-Jun Wu

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

公开(公告)号：US10861547B1

公开(公告)日：2020-12-08

申请号：US16417705

申请日：2019-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Cheng-Jun Wu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00

Abstract: In some embodiments, the present disclosure relates to a method of operation a resistive random access memory (RRAM) cell, comprising the performing of a reset operation to the RRAM cell. A first voltage bias is applied to the RRAM cell. The first voltage bias has a first polarity. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance. The intermediate resistance is greater than the low resistance. A second voltage bias is then applied to the RRAM cell. The second voltage bias has a second polarity that is opposite to the first polarity. The application of the second voltage bias induces the RRAM cell to have a high resistance. The high resistance is greater than the intermediate resistance.

公开(公告)号：US20200372955A1

公开(公告)日：2020-11-26

申请号：US16417705

申请日：2019-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Cheng-Jun Wu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: G11C13/00

Abstract: In some embodiments, the present disclosure relates to a method of operation a resistive random access memory (RRAM) cell, comprising the performing of a reset operation to the RRAM cell. A first voltage bias is applied to the RRAM cell. The first voltage bias has a first polarity. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance. The intermediate resistance is greater than the low resistance. A second voltage bias is then applied to the RRAM cell. The second voltage bias has a second polarity that is opposite to the first polarity. The application of the second voltage bias induces the RRAM cell to have a high resistance. The high resistance is greater than the intermediate resistance.

公开(公告)号：US20190058007A1

公开(公告)日：2019-02-21

申请号：US15678557

申请日：2017-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yang Tsai ,  Kuo-Ching Huang ,  Tong-Chern Ong

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The present disclosure relates to a memory circuit having a shared control device for access to target and complementary memory devices for improved differential sensing. The memory circuit has a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal. A first memory device has a first lower electrode separated from a first upper electrode by a first data storage layer. The first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line. A second memory device has a second lower electrode separated from a second upper electrode by a second data storage layer. The second upper electrode is coupled to the second bit-line and the second lower electrode is coupled to the third terminal.

公开(公告)号：US09893122B2

公开(公告)日：2018-02-13

申请号：US15292334

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang

IPC: G11C11/00 ,  H01L27/24 ,  G11C13/00 ,  H01L23/528 ,  H01L45/00 ,  H01L27/10

CPC classification number: H01L27/2463 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

公开(公告)号：US09472596B2

公开(公告)日：2016-10-18

申请号：US14967697

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang

IPC: G11C11/00 ,  H01L27/24 ,  G11C13/00 ,  H01L23/528 ,  H01L45/00

CPC classification number: H01L27/2463 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

Abstract translation: 一些实施例涉及包括设置在半导体衬底上的存储器单元阵列的集成电路器件。 第一金属线阵列被布置在衬底上的第一高度处并连接到阵列的存储器单元。 每个第一金属线具有第一横截面积。 第二金属线阵列设置在衬底上的第二高度处，并连接到阵列的存储单元。 每个第二金属线具有大于第一横截面积的第二横截面积。

公开(公告)号：US20210242400A1

公开(公告)日：2021-08-05

申请号：US17233755

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Yang Chen ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Wen-Ting Chu ,  Pili Huang ,  Cheng-Jun Wu

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.

公开(公告)号：US20210098630A1

公开(公告)日：2021-04-01

申请号：US17117711

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mickey Hsieh ,  Chun-Yang Tsai ,  Kuo-Ching Huang ,  Kuo-Chi Tu ,  Pili Huang ,  Cheng-Jun Wu ,  Chao-Yang Chen

IPC: H01L29/78 ,  H01L27/11507 ,  H01L49/02 ,  H01L29/66 ,  H01L29/51 ,  H01L27/1159 ,  H01L21/28

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

公开(公告)号：US20170092748A1

公开(公告)日：2017-03-30

申请号：US15371801

申请日：2016-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/732 ,  G11C13/00 ,  H01L27/24 ,  G11C11/16 ,  H01L29/66 ,  H01L27/22

CPC classification number: H01L29/732 ,  G11C11/161 ,  G11C11/40 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/226 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2454 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/82 ,  H01L45/04

Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

公开(公告)号：US09230647B2

公开(公告)日：2016-01-05

申请号：US14152244

申请日：2014-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yang Tsai ,  Yu-Wei Ting ,  Kuo-Ching Huang

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L27/2463 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes an array of RRAM cells, an array of bit lines for the array of RRAM cells, and an array of source lines for the array of RRAM cells. Both the source lines and the bit lines are in metal interconnect layers above the RRAM cells. The source line are thereby provided with a higher than conventional wire size, which increases the reset speed by approximately one order of magnitude. The lifetime of the RRAM transistors and the durability of the RRAM device are consequentially improved to a similar degree.

Abstract translation: 集成电路设备包括RRAM单元阵列，RRAM单元阵列的位线阵列，以及RRAM单元阵列的源极阵列。 源极线和位线都位于RRAM单元上方的金属互连层中。 因此，源极线被提供有高于常规电线尺寸，其将复位速度提高约一个数量级。 RRAM晶体管的寿命和RRAM器件的耐用性因此相应地得到改善。