公开(公告)号：US10777480B2

公开(公告)日：2020-09-15

申请号：US16705469

申请日：2019-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L29/40 ,  H01L29/41 ,  H01L23/29 ,  H01L23/532

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US10685885B2

公开(公告)日：2020-06-16

申请号：US15943671

申请日：2018-04-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds the active area of the substrate. The gate structure is across the active area of the substrate. The isolation structure has a first portion under the gate structure and a second portion adjacent to the gate structure. A top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.

公开(公告)号：US10515866B2

公开(公告)日：2019-12-24

申请号：US16218842

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L29/40 ,  H01L29/41 ,  H01L23/29 ,  H01L23/532

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US10461169B2

公开(公告)日：2019-10-29

申请号：US15911884

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei Yeh ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/285 ,  H01L23/485

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.

公开(公告)号：US09935013B2

公开(公告)日：2018-04-03

申请号：US14248755

申请日：2014-04-09

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0607 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621

Abstract: A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The effective gate length or the effective channel width of the device is increased by lowering a top surface of an oxide isolation structure below the gate of the semiconductor device.

公开(公告)号：US20180012818A1

公开(公告)日：2018-01-11

申请号：US15714099

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/31 ,  H01L29/40 ,  H01L23/00 ,  H01L23/29 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/482 ,  H01L23/532

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US09842768B2

公开(公告)日：2017-12-12

申请号：US15489947

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Cheng Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer and a first conductive structure over a substrate. The first dielectric layer surrounds the first conductive structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the first conductive structure. The method includes forming a seal layer over the first conductive structure and an inner wall of the opening. The seal layer is in direct contact with the first dielectric layer and the second dielectric layer, and the seal layer includes a dielectric material comprising an oxygen compound. The method includes removing the seal layer over the first conductive structure. The method includes filling a second conductive structure into the opening.

公开(公告)号：US09773716B2

公开(公告)日：2017-09-26

申请号：US15146012

申请日：2016-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/528 ,  H01L29/40 ,  H01L23/29 ,  H01L23/532

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate. The layer includes an opening extending through the layer. A plurality of bar or pillar structures or a tapered region are arranged in a peripheral portion of the opening and laterally surround a central portion of the opening. A metal body extends through the central portion of the opening.

公开(公告)号：US09299658B2

公开(公告)日：2016-03-29

申请号：US14717995

申请日：2015-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L23/525 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/167

CPC classification number: H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with the metal fuse and a fabricating method thereof are provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

Abstract translation: 提供了具有金属熔断器的半导体器件及其制造方法。 金属熔断器连接电子部件（例如，晶体管）和接地的现有虚拟特征。 金属保险丝的保护可以设计为在金属化形成工艺开始时开始。 接地的虚拟特征提供了在线路过程的整个后端期间等离子体对地面充电的路径。 金属保险丝是与二极管相反的过程电平保护，这是电路级保护。 作为工艺级保护，金属保险丝保护随后形成的电路。 此外，除了已经实现的内部虚拟图案之外，芯片中的金属熔断器不需要额外的有源区域。

公开(公告)号：US20150069395A1

公开(公告)日：2015-03-12

申请号：US14024688

申请日：2013-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Wei Yang ,  Yi-Ruei Lin ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/544 ,  H01L29/08 ,  H01L21/66

CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.

Abstract translation: 集成电路包括布置在硅衬底上的多个横向扩散测量结构。 横向扩散测量结构包括p型区域和n型区域，其协作地跨越横向扩散测量结构的相对外边缘之间的预定初始距离。 在发生掺杂剂扩散之后，p型和n型区域在预期位于目标连接位置处的p-n结处相交。