公开(公告)号：US20190207035A1

公开(公告)日：2019-07-04

申请号：US16353290

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Miin-Jang Chen ,  Chi-Wen Liu ,  Bo-Ting Lin

IPC: H01L29/78 ,  H01L27/1159 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L29/78391 ,  H01L21/02189 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28291 ,  H01L27/11521 ,  H01L27/1159 ,  H01L28/60 ,  H01L29/516 ,  H01L29/6684

Abstract: A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.

公开(公告)号：US10297548B2

公开(公告)日：2019-05-21

申请号：US15382492

申请日：2016-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768 ,  H01L21/3065 ,  H01L23/528 ,  H01L21/285 ,  H01L23/485 ,  H01L29/417

Abstract: A semiconductor device includes a semiconductor substrate, an epitaxy structure present in the semiconductor substrate, and a silicide present on a textured surface of the epitaxy structure. A plurality of sputter ions are present between the silicide and the epitaxy structure. Since the surface of the epitaxy structure is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.

公开(公告)号：US20190088757A1

公开(公告)日：2019-03-21

申请号：US16195591

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Che-Wei Yang ,  Chi-Wen Liu ,  Hao-Hsiung Lin ,  Ling-Yen Yeh

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/06 ,  H01L21/20 ,  H01L27/12

Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.

公开(公告)号：US10164059B2

公开(公告)日：2018-12-25

申请号：US14994057

申请日：2016-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Ming Peng ,  Chi-Wen Liu ,  Hsin-Chieh Huang ,  Yi-Ju Hsu ,  Horng-Huei Tseng

IPC: H01L21/70 ,  H01L29/66 ,  H01L29/78

Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.

公开(公告)号：US10141412B2

公开(公告)日：2018-11-27

申请号：US15333442

申请日：2016-10-25

Applicant: National Taiwan University ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yuh-Renn Wu ,  Chi-Wen Liu ,  Shou-Fang Chen

IPC: H01L29/06 ,  H01L29/772 ,  H01L29/24 ,  H01L29/04 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A field effect transistor (FET) includes a gate dielectric layer, a two-dimensional (2D) channel layer formed on the gate dielectric layer and a gate electrode. The 2D channel layer includes a body region having a first side and a second side opposite to the first side, the body region being a channel of the FET. The 2D channel layer further includes first finger regions each protruding from the first side of the body region and second finger regions each protruding from the second side of the body region. A source electrode covers the first finger regions, and a drain electrode covers the second finger regions.

公开(公告)号：US10068995B2

公开(公告)日：2018-09-04

申请号：US15210388

申请日：2016-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  National Taiwan University

Inventor： Fang-Liang Lu ,  CheeWee Liu ,  Chi-Wen Liu ,  Shih-Hsien Huang ,  I-Hsieh Wong

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/268 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78

Abstract: In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from an isolation insulating layer disposed over a substrate. A gate structure is formed over a part of the fin structure, thereby defining a channel region, a source region and a drain region in the fin structure. After the gate structure is formed, laser annealing is performed on the fin structure.

公开(公告)号：US10062735B2

公开(公告)日：2018-08-28

申请号：US15347255

申请日：2016-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Ting ,  Chi-Wen Liu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/66 ,  H01L27/24 ,  H01L27/22 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/2454 ,  H01L27/228 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments of the present disclosure relate to an integrated chip having a vertical transistor device. The integrated chip may have a semiconductor body with a trench extending along first sides of a source region, a channel region over the source region, and a drain region over the channel region. A gate electrode is arranged along a first sidewall of the trench, and a metal contact is arranged on the drain region. An isolation dielectric material is disposed within the trench. The isolation dielectric material is vertically over a top surface of the gate electrode and is laterally adjacent to the gate electrode.

公开(公告)号：US10050030B2

公开(公告)日：2018-08-14

申请号：US14990603

申请日：2016-01-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Chien Huang ,  Chi-Wen Liu ,  Horng-Huei Tseng ,  Tsung-Yu Chiang

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/306 ,  H01L49/02 ,  H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

公开(公告)号：US09577049B1

公开(公告)日：2017-02-21

申请号：US14989259

申请日：2016-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Shih-Yen Lin ,  Chong-Rong Wu ,  Chi-Wen Liu

IPC: H01L29/24 ,  H01L29/45 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/443

CPC classification number: H01L21/443 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78681

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a semiconductor layer over the substrate. The semiconductor layer includes a transition metal chalcogenide. The semiconductor device structure includes a source electrode and a drain electrode over and connected to the semiconductor layer and spaced apart from each other by a gap. The source electrode and the drain electrode are made of graphene.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括衬底。 半导体器件结构包括在衬底上的半导体层。 半导体层包括过渡金属硫族化物。 半导体器件结构包括在半导体层之上并连接到半导体层并且通过间隙彼此间隔开的源电极和漏电极。 源电极和漏电极由石墨烯制成。

公开(公告)号：US09520446B2

公开(公告)日：2016-12-13

申请号：US14450809

申请日：2014-08-04

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu-Wei Ting ,  Chi-Wen Liu ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC: H01L29/66 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L27/2454 ,  H01L27/228 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array.

Abstract translation: 本公开的一些实施例涉及包括具有垂直栅极全周（GAA）选择晶体管的存储器单元的存储器阵列。 在一些实施例中，存储器阵列具有设置在半导体本体的上表面内的源极区域和从半导体本体的上表面向外延伸并具有沟道区域和上覆漏极区域的半导体材料的半导体柱。 栅极区域通过栅极介电层在与沟道区域的侧壁横向分离的位置处垂直地覆盖源极区域。 第一金属触点将漏极区域耦合到存储数据的数据存储元件。 垂直GAA选择晶体管提供良好的性能，同时相对于平面MOSFET减小选择晶体管的尺寸，使得选择晶体管不会对存储器阵列的尺寸产生负面影响。