公开(公告)号：US12166128B2

公开(公告)日：2024-12-10

申请号：US18360344

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US20230369500A1

公开(公告)日：2023-11-16

申请号：US18360344

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/76816 ,  H01L23/5329 ,  H01L23/528 ,  H01L23/5226 ,  H01L21/76804 ,  H01L27/0924 ,  H01L21/823821

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US11777035B2

公开(公告)日：2023-10-03

申请号：US17849995

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7851 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/823821 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5329 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US20230260832A1

公开(公告)日：2023-08-17

申请号：US17831884

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kai Lin ,  Po-Cheng Shih ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76829 ,  H01L21/0228 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53266

Abstract: Semiconductor devices and methods of manufacture are presented herein in which a etch stop layer is selectively deposited over a conductive contact. A dielectric layer is formed over the etch stop layer and an opening is formed through the dielectric layer and the etch stop layer to expose the conductive contact. Conductive material is then deposited to fill the opening.

公开(公告)号：US11482493B2

公开(公告)日：2022-10-25

申请号：US17077556

申请日：2020-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Chun Wang ,  Chung-Chi Ko ,  Po-Cheng Shih

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.

公开(公告)号：US11417602B2

公开(公告)日：2022-08-16

申请号：US16919234

申请日：2020-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Cheng Shih ,  Chia Cheng Chou ,  Li Chun Te

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/522

Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.

公开(公告)号：US09768061B1

公开(公告)日：2017-09-19

申请号：US15168596

申请日：2016-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Cheng Shih ,  Chia Cheng Chou ,  Chung-Chi Ko

IPC: H01L21/768

CPC classification number: H01L21/76825 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76802

Abstract: A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask.

公开(公告)号：US20240395939A1

公开(公告)日：2024-11-28

申请号：US18790280

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Jen Chang ,  Chih-Chien Chi ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Kai-Shiang Kuo ,  Po-Cheng Shih ,  Jun-Yi Ruan

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/66

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

公开(公告)号：US20240120236A1

公开(公告)日：2024-04-11

申请号：US18306716

申请日：2023-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Jung Kuo ,  Po-Cheng Shih ,  Wan Chen Hsieh ,  Zhen-Cheng Wu ,  Chia-Hui Lin ,  Tze-Liang Lee

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/823481 ,  H01L27/0886

Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.

公开(公告)号：US20230317469A1

公开(公告)日：2023-10-05

申请号：US17711885

申请日：2022-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bor Chiuan Hsieh ,  Po-Hsien Cheng ,  Tsai-Jung Ho ,  Po-Cheng Shih ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L21/311 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/31144 ,  H01L21/76802 ,  H01L29/66795 ,  H01L29/6653 ,  H01L29/456 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76897

Abstract: A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric. In another embodiment, the method further includes forming a gate spacer over the substrate, wherein the etching the portion of the gate structure further comprises etching a portion of the gate spacer.