公开(公告)号：US08669607B1

公开(公告)日：2014-03-11

申请号：US13666712

申请日：2012-11-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yong-Shiuan Tsair ,  Wen-Ting Chu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Hsiang Yang ,  Chieh-Fei Chiu ,  Yu-Ling Hsu

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/11517 ,  H01L29/42328 ,  H01L29/7881

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Abstract translation: 提高编程效率的非易失性存储单元的方法和装置。 公开了一种装置，其包括形成在半导体衬底上形成的浮动栅极的一部分上的控制栅极。 所述控制栅极包括邻近所述半导体衬底中的源极区域的源极侧壁间隔壁和漏极侧壁间隔物，所述浮动栅极具有邻近所述源极区域的未被所述控制栅极覆盖的上表面部分; 在源极侧壁间隔物上的多晶硅电介质和邻近源极区域的浮置栅极的上表面; 以及擦除栅极，形成在源极区域上并且覆盖多晶硅电介质并且邻近控制栅极的源极侧壁，擦除栅极覆盖邻近源极区域的浮置栅极的上表面的至少一部分。 提供了形成装置的方法。

公开(公告)号：US12167611B2

公开(公告)日：2024-12-10

申请号：US18357240

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsiang Chang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Tzu-Yu Chen ,  Fu-Chen Chang

IPC: H10B51/00 ,  G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B53/30

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

公开(公告)号：US12161056B2

公开(公告)日：2024-12-03

申请号：US17411485

申请日：2021-08-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chieh-Fei Chiu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair ,  Yu-Wen Liao ,  Chin-Yu Mei ,  Po-Hao Tseng

IPC: H10N70/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.

公开(公告)号：US20240188454A1

公开(公告)日：2024-06-06

申请号：US18443368

申请日：2024-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10B63/00 ,  H10B63/30 ,  H10N70/011 ,  H10N70/063 ,  H10N70/066 ,  H10N70/24 ,  H10N70/801 ,  H10N70/826 ,  H10N70/8833

Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

公开(公告)号：US11894267B2

公开(公告)日：2024-02-06

申请号：US17141852

申请日：2021-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsia-Wei Chen ,  Fu-Ting Sung ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Fa-Shen Jiang ,  Tzu-Hsuan Yeh

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76832 ,  H01L23/528 ,  H01L23/53209

Abstract: A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.

公开(公告)号：US11889705B2

公开(公告)日：2024-01-30

申请号：US17392555

申请日：2021-08-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L23/522 ,  H01L23/528 ,  H10B63/00 ,  H10B10/10 ,  H10B99/00 ,  H10N70/00

CPC classification number: H10B63/80 ,  H01L23/528 ,  H01L23/5226 ,  H10B10/10 ,  H10B63/30 ,  H10B99/00 ,  H10N70/021 ,  H10N70/063 ,  H10N70/826 ,  H10N70/8833

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.

公开(公告)号：US11839090B2

公开(公告)日：2023-12-05

申请号：US17342731

申请日：2021-06-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L29/06 ,  H10B63/00 ,  H10B53/30 ,  H10B61/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10B63/80 ,  H10B53/30 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N70/011

Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.

公开(公告)号：US11800720B2

公开(公告)日：2023-10-24

申请号：US17528611

申请日：2021-11-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Chih-Hsiang Chang ,  Fu-Chen Chang

IPC: H10B53/00 ,  G11C11/22 ,  H10B53/10 ,  H10B53/30 ,  H01L49/02

CPC classification number: H10B53/00 ,  G11C11/221 ,  H01L28/55 ,  H01L28/60 ,  H10B53/10 ,  H10B53/30

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.

公开(公告)号：US11785777B2

公开(公告)日：2023-10-10

申请号：US17574010

申请日：2022-01-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsiang Chang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Tzu-Yu Chen ,  Fu-Chen Chang

IPC: H01L21/02 ,  H10B51/00 ,  G11C11/22 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

CPC classification number: H10B51/00 ,  G11C11/223 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

公开(公告)号：US11751485B2

公开(公告)日：2023-09-05

申请号：US17537830

申请日：2021-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tung-Sheng Hsiao ,  Wen-Ting Chu ,  Yu-Wen Liao ,  I-Ching Chen

IPC: H10N50/80 ,  H01L23/538 ,  H01L21/768 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N50/80 ,  H01L21/768 ,  H01L23/5384 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N50/10 ,  H10N70/011 ,  H10N70/20 ,  H10N70/841 ,  H10N70/8833

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.