公开(公告)号：US20180068050A1

公开(公告)日：2018-03-08

申请号：US15258932

申请日：2016-09-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng LIN ,  Chih-Liang CHEN ,  Chih-Ming LAI ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Ru-Gun LIU ,  Shih-Wei PENG ,  Wei-Chen CHIEN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072

Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.

公开(公告)号：US20170317089A1

公开(公告)日：2017-11-02

申请号：US15362002

申请日：2016-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Charles Chew-Yuen YOUNG ,  Chin-Yuan TSENG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Ru-Gun LIU ,  Wei-Liang LIN ,  L. C. CHOU

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308

CPC classification number: H01L27/1104 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886

Abstract: A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and capped semiconductor fins, the capped semiconductor fins being organized into at least first and second sets, with each member of the first set having a first cap with a first etch sensitivity, and each member of the second set having a second cap with a second etch, the second etch sensitivity being different than the first etch sensitivity; removing selected members of the first set and selected members of the second set from the structure.

公开(公告)号：US20240387361A1

公开(公告)日：2024-11-21

申请号：US18789538

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit includes a first conductive line parallel to a top surface of the substrate; a second conductive line parallel to the top surface of the substrate; a third conductive line parallel to the top surface of the substrate; and a fourth conductive line parallel to the top surface of the substrate. The integrated circuit further includes a first supervia directly connected to the first conductive line and the third conductive line, wherein a first angle between a lower sidewall of a lower portion of the first supervia and the top surface of the substrate is different from a second angle between an upper sidewall of an upper portion of the first supervia and the top surface of the substrate. The integrated circuit further includes a second supervia directly connecting the second conductive line to the fourth conductive line.

公开(公告)号：US20240266346A1

公开(公告)日：2024-08-08

申请号：US18639465

申请日：2024-04-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng Tzeng ,  Wei-Cheng Lin

IPC: H01L27/02 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H03K3/037

CPC classification number: H01L27/0207 ,  H01L21/84 ,  H01L27/12 ,  H03K3/037 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11887

Abstract: An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.

公开(公告)号：US20240258311A1

公开(公告)日：2024-08-01

申请号：US18588942

申请日：2024-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Te-Hsin CHIU ,  Kam-Tou SIO ,  Shang-Wei FANG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L27/088 ,  G06F30/392 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G06F30/392 ,  H01L21/0334 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.

公开(公告)号：US20230401372A1

公开(公告)日：2023-12-14

申请号：US18448136

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shang-Wei FANG ,  Kam-Tou SIO ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG ,  Lee-Chung LU ,  Yi-Kan CHENG ,  Chung-Hsing WANG

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: An integrated circuit (IC) includes first through fourth nano-sheet structures extending in a first direction and having respective first through fourth widths along a second direction perpendicular to the first direction, and first through fourth via structures electrically connected to corresponding ones of the first through fourth nano-sheet structures. The second width has a value greater than that of the third width. A width of the second via structure along the second direction has a value greater than that of a width of the third via structure along the second direction. The second and third nano-sheet structures are positioned between the first and fourth nano-sheet structures. The second and third via structures are configured to electrically connect the second and third nano-sheet structures to a first portion of a back-side power distribution structure configured to carry one of a power supply voltage or a reference voltage. The first and fourth via structures are configured to electrically connect the first and fourth nano-sheet structures to a second portion of the back-side power distribution structure configured to carry the other of the power supply voltage or the reference voltage.

公开(公告)号：US20230335545A1

公开(公告)日：2023-10-19

申请号：US18341369

申请日：2023-06-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kam-Tou SIO ,  Chih-Liang CHEN ,  Hui-Ting YANG ,  Shun Li CHEN ,  Ko-Bin KAO ,  Chih-Ming LAI ,  Ru-Gun LIU ,  Charles Chew-Yuen YOUNG

IPC: H01L21/8234 ,  H01L29/417 ,  H01L21/3213 ,  H01L29/423 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H10B10/12

Abstract: A method (of manufacturing conductors for a semiconductor device) includes: forming active regions (ARs) in a first layer, the ARs extending in a first direction; forming a conductive layer over the first layer; forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other; removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.

公开(公告)号：US20230247817A1

公开(公告)日：2023-08-03

申请号：US18190670

申请日：2023-03-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Charles Chew-Yuen YOUNG ,  Chin-Yuan TSENG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Ru-Gun LIU ,  Wei-Liang LIN ,  L. C. CHOU

IPC: H10B10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/3083 ,  H01L21/3086 ,  H01L29/7851 ,  H01L29/66795 ,  H01L21/31144

Abstract: A method (of manufacturing fins for a semiconductor device) includes: forming semiconductor fins including ones thereof having a first cap with a first etch sensitivity (first capped fins) and second ones thereof having a second cap with a second etch sensitivity (second capped fins), the first and second etch sensitivities being different; and eliminating selected ones of the first capped fins and selected ones of the second capped fins.

公开(公告)号：US20220115324A1

公开(公告)日：2022-04-14

申请号：US17237530

申请日：2021-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Te-Hsin CHIU ,  Kam-Tou SIO ,  Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238

Abstract: An integrated circuit includes a first, second and third active region and a first, second and third conductive line. The first, second and third active regions extend in a first direction, and are on a first level of a front-side of a substrate. The second active region is between the first active region and the third active region. The first and second conductive line extend in the first direction, and are on a second level of a back-side of the substrate. The first conductive line is between the first and second active region. The second conductive line is between the second and third active region. The third conductive line extends in the second direction, is on a third level of the back-side of the substrate, overlaps the first and second conductive line, and electrically couples the first and second active regions.

公开(公告)号：US20220068791A1

公开(公告)日：2022-03-03

申请号：US17123664

申请日：2020-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Te-Hsin CHIU ,  Wei-An LAI ,  Meng-Hung SHEN ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG ,  Kam-Tou SIO

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first metal line over the substrate and extending along a first direction, a protection layer lining a sidewall of the first metal line, a second metal line above the first metal line and extending along the first direction, and a third metal line above the second metal line, extending along a second direction perpendicular to the first direction.