公开(公告)号：US09922712B2

公开(公告)日：2018-03-20

申请号：US15436831

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau

IPC: G11C11/34 ,  G11C16/04 ,  H01L27/11521 ,  H01L27/11556 ,  G11C16/14 ,  G11C16/12 ,  G11C16/26

CPC classification number: G11C16/0433 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

公开(公告)号：US09876122B2

公开(公告)日：2018-01-23

申请号：US15365768

申请日：2016-11-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11553 ,  G11C16/14 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11556

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

公开(公告)号：US11424342B2

公开(公告)日：2022-08-23

申请号：US16939767

申请日：2020-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Franck Julien

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78

Abstract: In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.

公开(公告)号：US11270886B2

公开(公告)日：2022-03-08

申请号：US17009293

申请日：2020-09-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A MOS transistor is produced on and in an active zone and included a source region and a drain region. The active zone has a width measured transversely to a source-drain direction. A conductive gate region of the MOS transistor includes a central zone and, at a foot of the central zone, at least one stair that extends beyond the central zone along at least an entirety of the width of the active zone.

公开(公告)号：US10930351B2

公开(公告)日：2021-02-23

申请号：US16441378

申请日：2019-06-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  H01L29/423 ,  G11C16/12 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  G11C16/10

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

公开(公告)号：US20190341390A1

公开(公告)日：2019-11-07

申请号：US16391768

申请日：2019-04-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H01L27/1157 ,  H01L27/11565 ,  G11C5/06

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

公开(公告)号：US10192999B2

公开(公告)日：2019-01-29

申请号：US15852826

申请日：2017-12-22

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11553 ,  G11C16/14 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11556

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

公开(公告)号：US20190006008A1

公开(公告)日：2019-01-03

申请号：US16126316

申请日：2018-09-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau

IPC: G11C16/04 ,  H01L29/423 ,  H01L27/11556 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/14 ,  G11C16/12 ,  G11C16/10

CPC classification number: G11C16/0433 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

公开(公告)号：US20180040376A1

公开(公告)日：2018-02-08

申请号：US15436831

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  G11C16/12 ,  H01L27/11521 ,  H01L27/11556

CPC classification number: G11C16/0433 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336

Abstract: A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable.

公开(公告)号：US09570513B2

公开(公告)日：2017-02-14

申请号：US14150596

申请日：2014-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/108 ,  H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L29/08

CPC classification number: H01L27/2445 ,  H01L27/226 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/04 ,  H01L45/06 ,  H01L45/16

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

Abstract translation: 本公开涉及包括晶体管的集成电路，该晶体管包括第一和第二导电端子以及控制端子。 集成电路还包括第一介电层，导电层和第二介电层的堆叠，第一导电端子包括形成在第一介电层中的第一半导体区域，该控制端子包括形成在第一介电层中的第二半导体区域 导电层，第二导电端子包括形成在第二介电层中的第三半导体区域。