-
公开(公告)号：US10339080B2
公开(公告)日：2019-07-02
申请号：US15188347
申请日：2016-06-21
Applicant: SK hynix Inc.
Inventor： Hyung-Gyun Yang , Yong-Ju Kim , Yong-Kee Kwon , Hong-Sik Kim
Abstract: A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.
-
公开(公告)号：US10256823B2
公开(公告)日：2019-04-09
申请号：US16106658
申请日：2018-08-21
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Dae-Han Kwon , Shin-Deok Kang
Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.
-
公开(公告)号：US09842644B1
公开(公告)日：2017-12-12
申请号：US15596828
申请日：2017-05-16
Applicant: SK hynix Inc.
Inventor： Yong-Ju Kim , Sang-Gu Jo
CPC classification number: G11C13/0033 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/76
Abstract: A method for operating a memory device comprising a plurality of memory cells, the method may include: performing a first refresh operation comprising sequentially applying a recovery pulse to each of the plurality of memory cells and repeating the sequential application of the recovery pulse to each of the plurality of memory cells for a predetermined number of times; and performing a second refresh operation comprising sequentially re-writing data of each of the plurality of memory cells once after the first refresh operation is performed for the predetermined number of times.
-
公开(公告)号：US20170017410A1
公开(公告)日：2017-01-19
申请号：US14981387
申请日：2015-12-28
Applicant: SK hynix Inc.
Inventor： Jong-Bum Park , Yong-Kee Kwon , Yong-Ju Kim
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0631 , G06F3/0644 , G06F3/0653 , G06F3/0688
Abstract: A memory controller includes: a write performance storage circuit suitable for storing write performance indexes of physical memory areas of a memory device, a write counting circuit suitable for counting a number of requests of a write operation on logical memory areas of the memory device, and a mapping circuit suitable for mapping a logical memory area, for which the number of requests of the write operation r may be relatively large, to a physical memory area with a better write performance index.
Abstract translation: 存储器控制器包括：写入性能存储电路，适用于存储存储器件的物理存储器区域的写入性能指标;写入计数电路，用于对存储器件的逻辑存储器区域上的写入操作的数量进行计数;以及 适于将写入操作r的请求数量可能相对较大的逻辑存储器区域映射到具有更好的写入性能指数的物理存储器区域的映射电路。
-
公开(公告)号：US09490853B2
公开(公告)日：2016-11-08
申请号：US14856409
申请日：2015-09-16
Inventor： Kang-Sub Kwak , Jong-Hyun Ra , Oh-Kyong Kwon , Hae-Rang Choi , Yong-Ju Kim
Abstract: A data transmitter may include a transmitter circuit and a calibration controller. The transmitter circuit is configured to be coupled to a receiver through a channel, and configured to provide an output signal to the channel based on an input signal and adjust an output impedance value according to a bias signal. The calibration controller is configured to adjust the bias signal by comparing the output signal of the transmitter circuit to a reference signal during a calibration operation.
Abstract translation: 数据发射机可以包括发射机电路和校准控制器。 发射机电路被配置为通过信道耦合到接收机，并且被配置为基于输入信号向信道提供输出信号，并根据偏置信号调整输出阻抗值。 校准控制器被配置为通过在校准操作期间将发射机电路的输出信号与参考信号进行比较来调整偏置信号。
-
Patent Agency Ranking
26.发明授权Filtering circuit, phase identity determination circuit and delay locked loop 有权滤波电路，相位识别确定电路和延迟锁定环公开(公告)号：US09225346B2
公开(公告)日：2015-12-29
申请号：US14159193
申请日：2014-01-20
Applicant: SK hynix Inc.
Inventor： Dae-Han Kwon , Yong-Ju Kim , Taek-Sang Song
CPC classification number: H03L7/093 , H03L7/0812 , H03L7/235
Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
Abstract translation: 滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为滤波输入信号并生成滤波的 信号与操作时钟同步。
-
27.发明授权公开(公告)号：US08866526B2
公开(公告)日：2014-10-21
申请号：US14133063
申请日：2013-12-18
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim
CPC classification number: H03K5/1565 , H03K21/38
Abstract: A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.
-
公开(公告)号：US08686768B2
公开(公告)日：2014-04-01
申请号：US13844865
申请日：2013-03-16
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Jae-Min Jang
IPC: H03L7/06
Abstract: A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.
Abstract translation: 锁相环包括相位检测器，被配置为将输入时钟的相位与反馈时钟的相位进行比较以产生相位比较结果，初始频率值提供器被配置为检测输入时钟的频率并提供频率检测 结果，配置为基于相位比较结果和频率检测结果产生频率控制信号的控制器，以及响应于频率控制信号产生输出时钟的振荡器。
-
公开(公告)号：US20130076401A1
公开(公告)日：2013-03-28
申请号：US13680239
申请日：2012-11-19
Applicant: SK HYNIX INC.
Inventor： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC: H03K5/153
CPC classification number: H03K5/153
Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。
-
公开(公告)号：US10936481B2
公开(公告)日：2021-03-02
申请号：US15682705
申请日：2017-08-22
Applicant: SK hynix Inc.
Inventor： Yong-Ju Kim , Dong-Gun Kim , Do-Sun Hong
Abstract: A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.
-
-
-
-
-
-
-
-
-
Search Results
35
records
(took 0.018 seconds)
