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28 条记录 (耗时 0.016 秒)

    Memory system and operating method thereof
    1.
    发明授权
    Memory system and operating method thereof 有权

    公开(公告)号：US11003531B2

    公开(公告)日：2021-05-11

    申请号：US16038792

    申请日：2018-07-18

    申请人： SK hynix Inc.

    发明人： Jung-Hyun Kwon ,  Do-Sun Hong ,  Seung-Gyu Jeong ,  Won-Gyu Shin

    IPC分类号： G06F11/10 ,  G06F11/00 ,  G11C29/52 ,  G11C29/42 ,  G11C29/04

    摘要： A memory system includes: a memory device, including a plurality of memory cells, suitable for reading and writing data with a parity bit on a basis of a page; and a memory controller suitable for obtaining an error mask pattern based on compressed data when a number of error bits detected based on the data and the parity bit is equal to or less than a first threshold value and greater than a second threshold value, and controlling to write the compressed data, the parity bit updated based on the compressed data in which the error mask pattern is reflected, compression information on the compressed data and pattern information on the error mask pattern to the page.

    Memory system and error correcting method thereof
    3.
    发明授权
    Memory system and error correcting method thereof 有权

    公开(公告)号：US10795763B2

    公开(公告)日：2020-10-06

    申请号：US16203862

    申请日：2018-11-29

    申请人： SK hynix Inc.

    发明人： Yong-Ju Kim ,  Do-Sun Hong ,  Dong-Gun Kim

    IPC分类号： G11C29/52 ,  G06F11/10 ,  G11C29/44 ,  G11C29/42 ,  H03M13/15 ,  G11C29/04

    摘要： A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.

    Delay circuit and write and read latency control circuit of memory, and signal delay method thereof
    8.
    发明授权
    Delay circuit and write and read latency control circuit of memory, and signal delay method thereof 有权

    公开(公告)号：US10762008B2

    公开(公告)日：2020-09-01

    申请号：US16203591

    申请日：2018-11-28

    申请人： SK hynix Inc.

    发明人： Jung-Hyun Kwon ,  Do-Sun Hong ,  Won-Gyu Shin ,  Seung-Gyu Jeong

    IPC分类号： G06F13/16 ,  G06F3/06

    摘要： A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.

    Memory system and method for wear-leveling by swapping memory cell groups
    9.
    发明授权
    Memory system and method for wear-leveling by swapping memory cell groups 有权

    公开(公告)号：US10360157B2

    公开(公告)日：2019-07-23

    申请号：US15597866

    申请日：2017-05-17

    申请人： SK hynix Inc.

    发明人： Dong-Gun Kim ,  Yong-Ju Kim ,  Sang-Gu Jo ,  Do-Sun Hong

    IPC分类号： G06F12/1027 ,  G06F12/1009

    摘要： A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.