公开(公告)号：US11501832B2

公开(公告)日：2022-11-15

申请号：US17205647

申请日：2021-03-18

申请人： SK hynix Inc.

发明人： Won Gyu Shin ,  Jung Hyun Kwon

IPC分类号： G11C7/10 ,  G11C13/00

摘要： According to an embodiment, a memory system comprises a resistive memory device configured to perform a read operation and a write operation based on a command and an address, wherein the resistive memory device includes a plurality of banks each including a plurality of memory cells; and a memory controller configured to schedule a request from a host to generate the command and the address, wherein, when a time interval is less than a first time, the memory controller is configured to stop generation of the command and re-schedule the command corresponding to the request, the time interval spanning from a time of generation of a prior write command for a same memory cell to a time of generation of the command generated according to the request.

公开(公告)号：US11037610B2

公开(公告)日：2021-06-15

申请号：US16210303

申请日：2018-12-05

申请人： SK hynix Inc.

发明人： Seunggyu Jeong ,  Jung Hyun Kwon ,  Wongyu Shin ,  Do Sun Hong

IPC分类号： G11C7/22 ,  G11C16/32 ,  G11C16/26 ,  G06F9/30 ,  G06F11/07 ,  G06F11/30 ,  G11C7/10

摘要： A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.

公开(公告)号：US10665297B2

公开(公告)日：2020-05-26

申请号：US16236000

申请日：2018-12-28

申请人： SK hynix Inc.

发明人： Do-Sun Hong ,  Jung Hyun Kwon ,  Won Gyu Shin ,  Seung Gyu Jeong

IPC分类号： G11C13/00 ,  G11C11/56 ,  G11C29/42 ,  G06F13/16 ,  G11C29/04

摘要： A memory system includes a memory device and a memory controller. The memory device has a plurality of memory regions. The memory controller is configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value.

公开(公告)号：US10114561B2

公开(公告)日：2018-10-30

申请号：US15493289

申请日：2017-04-21

申请人： SK hynix Inc.

发明人： Do-Sun Hong ,  Jung Hyun Kwon ,  Donggun Kim ,  Yong Ju Kim ,  Sungeun Lee ,  Jae Sun Lee ,  Sang Gu Jo ,  Jingzhe Xu

IPC分类号： G11C13/00 ,  G06F3/06 ,  G11C16/34 ,  G06F12/10 ,  G06F12/02

摘要： A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

公开(公告)号：US10083103B1

公开(公告)日：2018-09-25

申请号：US15823190

申请日：2017-11-27

申请人： SK hynix Inc.

发明人： Jung Hyun Kwon ,  Sungeun Lee ,  Sang Gu Jo

IPC分类号： G11C7/00 ,  G06F11/30 ,  H01L27/24 ,  G06F1/32 ,  G11C13/00 ,  H01L45/00 ,  G11C7/10

摘要： A circuit for calculating power consumption of a phase change memory (PCM) device may be provided. The circuit may include a plurality of pipelines and an arithmetic logic circuit. The plurality of pipelines may be configured to correspond to a plurality of write periods exhibiting different power consumption values during a write operation of the PCM device executed by a write command. The plurality of pipelines may shift or transmit data in synchronization with a clock signal. The arithmetic logic circuit may be configured to perform an adding operation of all of deviations of the power consumption values at a point of time that data transmission between at least two of the plurality of pipelines occurs, to thus generate a total power consumption value.

公开(公告)号：US11461022B2

公开(公告)日：2022-10-04

申请号：US17222429

申请日：2021-04-05

申请人： SK hynix Inc.

发明人： Won Gyu Shin ,  Jung Hyun Kwon

IPC分类号： G06F3/06 ,  G06F13/16

摘要： A memory system may comprise a memory; and a memory controller configured to issue, to the memory, commands scheduled in a first scheme when power consumption of the memory is less than a first threshold and commands scheduled in a second scheme when the power consumption is not less than the first threshold and less than a second threshold, and stop the issuance of the commands to the memory when the power consumption of the memory is not less than the second threshold.

公开(公告)号：US10776262B2

公开(公告)日：2020-09-15

申请号：US16169835

申请日：2018-10-24

申请人： SK hynix Inc.

发明人： Do-Sun Hong ,  Jung Hyun Kwon ,  Won Gyu Shin ,  Seung Gyu Jeong

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F3/06

摘要： A memory system may include a nonvolatile memory device and a wear leveling unit. The nonvolatile memory device includes a plurality of memory blocks. The wear leveling unit may be configured to intermittently increase an accumulative access count of a memory block among the memory blocks by a predetermined value, decide a wear level of the memory block based on the accumulative access count whenever the accumulative access count is increased, set the memory block to a hot block based on the wear level, and perform a hot block management operation on the hot block. The wear leveling unit may increase the accumulative access count in response to an access count reaching a predetermined value. The accumulative access count may be stored in the nonvolatile memory device, and the access count may be stored in a volatile memory device.

公开(公告)号：US10438655B2

公开(公告)日：2019-10-08

申请号：US15822718

申请日：2017-11-27

申请人： SK hynix Inc.

发明人： Donggun Kim ,  Jung Hyun Kwon ,  Yong Ju Kim ,  Do Sun Hong

IPC分类号： G11C11/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C7/10 ,  G06F12/02 ,  G11C16/08 ,  G11C13/00 ,  G11C16/34 ,  G11C7/12 ,  G11C8/08

摘要： An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.

公开(公告)号：US20180307411A1

公开(公告)日：2018-10-25

申请号：US15830426

申请日：2017-12-04

申请人： SK hynix Inc.

发明人： Donggun Kim ,  Jung Hyun Kwon

IPC分类号： G06F3/06 ,  G06F13/16

摘要： A scheduler of a memory system is provided. The scheduler may include a pattern storage part and a pattern selector. The pattern storage part may have a plurality of storage patterns, each of the storage patterns provide for a process sequence for a plurality of instructions. The pattern selector may be configured to select one of the plurality of storage patterns in the pattern storage part and generate a schedule such that external instructions are executed in the process sequence set by the selected storage pattern.

公开(公告)号：US10761747B2

公开(公告)日：2020-09-01

申请号：US15883953

申请日：2018-01-30

申请人： SK hynix Inc.

发明人： Do-Sun Hong ,  Jung Hyun Kwon ,  Seung Gyu Jeong ,  Won Gyu Shin

IPC分类号： G06F11/16 ,  G06F3/06 ,  G11C29/00

摘要： A memory device includes a memory region; and an access unit suitable for setting an offset value according to control of an external device, changing, in response to an access command of the external device for a first address of the memory region, the first address into a second address of the memory region based on the offset value, and performing an access operation for the second address.