知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

37 records (took 0.024 seconds)

    Simulation method and system
    21.
    发明授权
    Simulation method and system 有权

    公开(公告)号：US11010532B2

    公开(公告)日：2021-05-18

    申请号：US16794045

    申请日：2020-02-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Alexander Schmidt ,  Dong-Gwan Shin ,  Anthony Payet ,  Hyoung Soo Ko ,  Seok Hoon Kim ,  Hyun-Kwan Yu ,  Si Hyung Lee ,  In Kook Jang

    IPC: G06F30/367 ,  G06F30/398 ,  H01L27/02

    Abstract: A simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, imaging generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors (EDF) respectively for the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating first to m-th epitaxy times for first to m-th effective open silicon densities.

    BUS INTERFACE DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME
    26.
    发明申请
    BUS INTERFACE DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME 审中-公开
    总线接口装置，包括其的半导体集成电路装置及其操作方法

    公开(公告)号：US20160283416A1

    公开(公告)日：2016-09-29

    申请号：US15077553

    申请日：2016-03-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JIN SEOK HA ,  Seok Hoon Kim ,  Eui Cheol Lim ,  Jin Yong Jung

    IPC: G06F13/16 ,  G06F12/08

    CPC classification number: G06F13/1642 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/1673 ,  G06F2212/401 ,  G06F2212/455

    Abstract: A bus interface device for requesting and receiving data from a memory controller connected to a bus includes a request buffer and a request merger. The request buffer is configured to store a first data request signal for requesting first data and a second data request signal for requesting second data. The request merger is configured to determine whether to merge the first and second data request signals, and transmit a merged request signal for requesting the first data and the second data from the memory controller to the bus upon determining that the first and second data request signals are to be merged.

    Abstract translation: 用于从连接到总线的存储器控​​制器请求和接收数据的总线接口装置包括请求缓冲器和请求合并。 请求缓冲器被配置为存储用于请求第一数据的第一数据请求信号和用于请求第二数据的第二数据请求信号。 所述请求合并被配置为确定是否合并所述第一和第二数据请求信号，并且在确定所述第一数据请求信号和所述第二数据请求信号之后，将从所述存储器控制器请求所述第一数据和所述第二数据的合并请求信号发送到所述总线 将被合并。

    GRAPHICS PROCESSING UNIT, METHOD OF OPERATING THE SAME, AND DEVICES INCLUDING THE SAME
    27.
    发明申请
    GRAPHICS PROCESSING UNIT, METHOD OF OPERATING THE SAME, AND DEVICES INCLUDING THE SAME 有权
    图形处理单元，其操作方法和包括其的设备

    公开(公告)号：US20150042650A1

    公开(公告)日：2015-02-12

    申请号：US14447883

    申请日：2014-07-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seok Hoon Kim ,  Yong Ha Park ,  Chang Hyo Yu ,  Kil Whan Lee

    IPC: G06T15/08

    CPC classification number: G06T17/30 ,  G06T15/005 ,  G06T15/10 ,  G06T17/20

    Abstract: A method of operating a graphics processing unit includes determining, based on input data, whether to perform a tiling operation before or after a tessellation operation and performing the tiling operation according to the determination result. Performing the tiling operation after the tessellation operation if the input data is not a patch, and if a geometry of the patch is at the out-side of a convex hull defined by control points of the patch. Performing the tiling operation after the tessellation operation if a geometry of a tessellated primitive corresponding to the patch changes according to a shading operation.

    Abstract translation: 操作图形处理单元的方法包括：基于输入数据确定是否在细分操作之前或之后执行拼贴操作，并根据确定结果进行拼贴操作。 如果输入数据不是补丁，则在细分操作之后执行平铺操作，并且如果补丁的几何形状位于由补丁的控制点定义的凸包的外侧。 如果与补丁相对应的镶嵌图元的几何形状根据着色操作而变化，则在细分操作之后执行平铺操作。

    Semiconductor devices
    28.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US12142690B2

    公开(公告)日：2024-11-12

    申请号：US18588163

    申请日：2024-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

    Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

    Semiconductor device
    30.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12040402B2

    公开(公告)日：2024-07-16

    申请号：US17690178

    申请日：2022-03-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yang Xu ,  Nam Kyu Cho ,  Seok Hoon Kim ,  Yong Seung Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Sang Gil Lee ,  Si Hyung Lee

    IPC: H01L29/76 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/94

    CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791

    Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

Patent Agency Ranking