公开(公告)号：US10133685B2

公开(公告)日：2018-11-20

申请号：US15077553

申请日：2016-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Seok Ha ,  Seok Hoon Kim ,  Eui Cheol Lim ,  Jin Yong Jung

IPC: G06F13/14 ,  G06F13/16 ,  G06F12/084

Abstract: A bus interface device for requesting and receiving data from a memory controller connected to a bus includes a request buffer and a request merger. The request buffer is configured to store a first data request signal for requesting first data and a second data request signal for requesting second data. The request merger is configured to determine whether to merge the first and second data request signals, and transmit a merged request signal for requesting the first data and the second data from the memory controller to the bus upon determining that the first and second data request signals are to be merged.

公开(公告)号：US20160283416A1

公开(公告)日：2016-09-29

申请号：US15077553

申请日：2016-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN SEOK HA ,  Seok Hoon Kim ,  Eui Cheol Lim ,  Jin Yong Jung

IPC: G06F13/16 ,  G06F12/08

CPC classification number: G06F13/1642 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/1673 ,  G06F2212/401 ,  G06F2212/455

Abstract: A bus interface device for requesting and receiving data from a memory controller connected to a bus includes a request buffer and a request merger. The request buffer is configured to store a first data request signal for requesting first data and a second data request signal for requesting second data. The request merger is configured to determine whether to merge the first and second data request signals, and transmit a merged request signal for requesting the first data and the second data from the memory controller to the bus upon determining that the first and second data request signals are to be merged.

Abstract translation: 用于从连接到总线的存储器控​​制器请求和接收数据的总线接口装置包括请求缓冲器和请求合并。 请求缓冲器被配置为存储用于请求第一数据的第一数据请求信号和用于请求第二数据的第二数据请求信号。 所述请求合并被配置为确定是否合并所述第一和第二数据请求信号，并且在确定所述第一数据请求信号和所述第二数据请求信号之后，将从所述存储器控制器请求所述第一数据和所述第二数据的合并请求信号发送到所述总线 将被合并。

公开(公告)号：US09128633B2

公开(公告)日：2015-09-08

申请号：US14019807

申请日：2013-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eui Cheol Lim

IPC: G06F3/00 ,  G06F3/06 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0683 ,  G06F13/4239

Abstract: A method of operating a semiconductor memory device includes receiving a timeout index signal corresponding to a master of the first master group based on a residual capacity of a data buffer of the first master, setting a first timeout value in response to the timeout index signal, and changing an execution order of commands stored in a queue of the semiconductor memory device based on a result of counting the first timeout value and counting a second timeout value corresponding to a master of the second master group.

Abstract translation: 一种操作半导体存储器件的方法包括基于第一主器件的数据缓冲器的剩余容量来接收与第一主组的主器件对应的超时指示信号，响应于超时指示信号设置第一超时值， 以及基于对所述第一超时值进行计数的结果并且对与所述第二主组的主机相对应的第二超时值进行计数来改变存储在所述半导体存储器件的队列中的命令的执行顺序。