公开(公告)号：US12207456B2

公开(公告)日：2025-01-21

申请号：US18525187

申请日：2023-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

IPC: H10B12/00

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

公开(公告)号：US11665883B2

公开(公告)日：2023-05-30

申请号：US17202465

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inkyoung Heo ,  Hyo-Sub Kim ,  Sohyun Park ,  Taejin Park ,  Seung-Heon Lee ,  Youn-Seok Choi ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768 ,  H01L23/482 ,  H01L21/762

CPC classification number: H01L27/10814 ,  H01L21/7682 ,  H01L23/5329 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L21/76264 ,  H01L23/4821

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

公开(公告)号：US11616066B2

公开(公告)日：2023-03-28

申请号：US17384347

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US11600620B2

公开(公告)日：2023-03-07

申请号：US17353398

申请日：2021-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Il Han ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108

Abstract: A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

公开(公告)号：US11574915B2

公开(公告)日：2023-02-07

申请号：US17328228

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Choi ,  Woonghwi Bae ,  Jinwoo Bae ,  Chaelin Yoon ,  Sunghee Han ,  Sunwoo Heo ,  Deoksung Hwang

IPC: H01L27/108

Abstract: A semiconductor device includes first bit lines disposed on a substrate. Buried contacts disposed among first bit lines and connected to the substrate are provided. Landing pads are disposed on the buried contacts. Second bit lines are disposed on a peripheral area of the substrate. Upper surfaces of the second bit lines and the landing pads are coplanar with each other. First insulating patterns are disposed among the second bit lines. Second insulating patterns are disposed among the landing pads. Cell capacitors connected to the landing pads are disposed. The first insulating patterns include an insulating layer different from at least one insulating layer of the second insulating patterns.

公开(公告)号：US20220293420A1

公开(公告)日：2022-09-15

申请号：US17680996

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Keunnam Kim ,  Daehyoun Kim ,  Taejin Park ,  Sunghee Han

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311

Abstract: A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

公开(公告)号：US11322499B2

公开(公告)日：2022-05-03

申请号：US16943019

申请日：2020-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehwan Cho ,  Junghwan Oh ,  Sangho Lee ,  Junwon Lee ,  Jinwoo Bae ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108

Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

公开(公告)号：US11270885B2

公开(公告)日：2022-03-08

申请号：US16776948

申请日：2020-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Keunnam Kim ,  Daehyoun Kim ,  Taejin Park ,  Sunghee Han

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311

Abstract: A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

公开(公告)号：US11088143B2

公开(公告)日：2021-08-10

申请号：US16896470

申请日：2020-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US20190088739A1

公开(公告)日：2019-03-21

申请号：US15890707

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Myeong-Dong Lee ,  Hui-Jung Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Seokhan Park ,  Woosong Ahn ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L29/06 ,  H01L27/108 ,  H01L23/528 ,  H01L23/535

Abstract: A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.