公开(公告)号：US12218002B2

公开(公告)日：2025-02-04

申请号：US18537896

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin Kang ,  Jong Min Baek ,  Woo Kyung You ,  Kyu-Hee Han ,  Han Seong Kim ,  Jang Ho Lee ,  Sang Shin Jang

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US20230326964A1

公开(公告)日：2023-10-12

申请号：US18056736

申请日：2022-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong Kwan Baek ,  Jun Hyuk Lim ,  Jung Hwan Chun ,  Kyu-Hee Han ,  Jong Min Baek ,  Koung Min Ryu ,  Jung Hoo Shin ,  Sang Shin Jang

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L29/778

CPC classification number: H01L29/0673 ,  H01L29/778 ,  H01L29/78696 ,  H01L29/41733

Abstract: Semiconductor devices with improved performance and reliability and methods for forming the same are provided. The semiconductor devices include an active pattern extending in a first direction, gate structures spaced apart from each other in the first direction on the active pattern, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner extending along a sidewall of the source/drain contacts. A carbon concentration of the contact liner at a first point of the contact liner is different from a carbon concentration of the contact liner at a second point of the contact liner, and the first point is at a first height from an upper surface of the active pattern, the second point is at a second height from the upper surface of the active pattern, and the first height is smaller than the second height.

公开(公告)号：US11569128B2

公开(公告)日：2023-01-31

申请号：US17174409

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin Lee ,  Hoon Seok Seo ,  Sanghoon Ahn ,  Kyu-Hee Han

IPC: H01L23/528 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

公开(公告)号：US10669631B2

公开(公告)日：2020-06-02

申请号：US16031349

申请日：2018-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Chul Kim ,  Jung-Il Ahn ,  Jung-Hun Seo ,  Jong-Cheol Lee ,  Kyu-Hee Han ,  Seung-Han Lee ,  Jin-Pil Heo

IPC: C23C16/40 ,  C23C16/455 ,  C23C16/44

Abstract: A gas injection apparatus, which can sequentially supply a substrate with at least two kinds of source gases reacting with each other in a container, and thin film deposition equipment including the gas injection apparatus, are provided. The gas injection apparatus includes a base plate, a first gas supply region protruding from the base plate, a second gas supply region protruding from the base plate and adjacent the first gas supply region, and a trench defined by a sidewall of the first gas supply region and a sidewall of the second gas supply region. The sidewall of the first gas supply region and the sidewall of the second gas supply region face each other and extend in a radial direction on the base plate.

公开(公告)号：US20190043809A1

公开(公告)日：2019-02-07

申请号：US15909390

申请日：2018-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhee KANG ,  Jiyoung Kim ,  Taejin Yim ,  Jongmin Baek ,  Sanghoon Ahn ,  Hyeoksang Oh ,  Kyu-Hee Han

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/5329

Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.

公开(公告)号：US10199263B2

公开(公告)日：2019-02-05

申请号：US15616334

申请日：2017-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Shin Jang ,  Woo-Kyung You ,  Kyu-Hee Han ,  Jong-Min Baek ,  Viet Ha Nguyen ,  Byung-Hee Kim

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.

公开(公告)号：US09633836B2

公开(公告)日：2017-04-25

申请号：US14291670

申请日：2014-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon Ahn ,  Seung-Hyuk Choi ,  Kyu-Hee Han

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/02203 ,  H01L21/02126 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.

公开(公告)号：US09171781B2

公开(公告)日：2015-10-27

申请号：US14134043

申请日：2013-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Hee Lee ,  Jongmin Baek ,  Kyu-Hee Han ,  Gilheyun Choi ,  Jongwon Hong

IPC: H01L23/48 ,  H01L21/764 ,  H01L23/482 ,  H01L23/522 ,  H01L21/768 ,  H01L23/28

CPC classification number: H01L23/4821 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/28 ,  H01L23/48 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/0001

Abstract: Semiconductor devices, and methods of fabricating the same, include first conductive lines on a substrate, and a first molding layer covering the first conductive lines. The first conductive lines have air gaps between adjacent first conductive lines. Sidewalls of the first conductive lines and a bottom surface of the first molding layer collectively define a first gap region of each of the air gaps. The sidewalls of the first conductive lines and a top surface of the first molding layer collectively define a second air gap region of each of the air gaps.

Abstract translation: 半导体器件及其制造方法包括在基板上的第一导线和覆盖第一导线的第一成型层。 第一导线在相邻的第一导线之间具有气隙。 第一导电线的侧壁和第一模制层的底表面共同限定每个气隙的第一间隙区域。 第一导电线的侧壁和第一模制层的顶表面共同限定每个气隙的第二气隙区域。