公开(公告)号：US11462477B2

公开(公告)日：2022-10-04

申请号：US17082494

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin Shin ,  Minhyun Lee ,  Changseok Lee ,  Hyeonsuk Shin ,  Seokmo Hong

IPC: H01L23/532 ,  H01L23/522

Abstract: An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

公开(公告)号：US11424186B2

公开(公告)日：2022-08-23

申请号：US17082530

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Hyeonjin Shin ,  Minhyun Lee ,  Changseok Lee ,  Kyung-Eun Byun ,  Hyeonsuk Shin ,  Seokmo Hong

IPC: H01L23/532 ,  H01L23/522 ,  H01L27/108

Abstract: A semiconductor memory device and a device including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction crossing the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

公开(公告)号：US09997604B2

公开(公告)日：2018-06-12

申请号：US15113079

申请日：2015-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Lee ,  Changseok Lee ,  Seongjun Park

IPC: H01L29/417 ,  H01L29/78 ,  H01L23/532 ,  H01L21/768 ,  H01L29/16 ,  H01L23/522 ,  H01L23/485

CPC classification number: H01L29/41725 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53276 ,  H01L29/1606 ,  H01L29/417 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are an electrode connecting structure that includes an adhesion layer formed between a graphene layer and a metal layer and an electronic device having the electrode connecting structure. The electrode connecting structure may include an adhesion layer formed of a two-dimensional material provided between the graphene layer and the metal layer. The graphene layer may be a diffusion barrier, and the adhesion layer may stably maintain the interface characteristics of the graphene layer and the metal layer when the metal layer is formed on a surface of the graphene layer.

公开(公告)号：US09761532B2

公开(公告)日：2017-09-12

申请号：US15083827

申请日：2016-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook Shin ,  Hyeonjin Shin ,  Changhyun Kim ,  Changseok Lee ,  Seongjun Park ,  Hyunjae Song

IPC: H01L23/495 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53276 ,  H01L23/485 ,  H01L23/5283

Abstract: A hybrid interconnect structure includes a graphene layer between a non-metallic material layer and a metal layer, and a first interfacial bonding layer between the non-metallic material layer and the graphene layer, or the metal layer and the graphene layer. The graphene layer connects the non-metallic material layer and the metal layer, and the first bonding layer includes a metallic material.

公开(公告)号：US12272402B2

公开(公告)日：2025-04-08

申请号：US17708362

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun Lee ,  Taein Kim ,  Youngtek Oh ,  Hyeonjin Shin ,  Changseok Lee

IPC: G11C16/04 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20 ,  H10B43/35

Abstract: Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

公开(公告)号：US12211904B2

公开(公告)日：2025-01-28

申请号：US17398515

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Minsu Seol ,  Hyeonsuk Shin ,  Hyeonjin Shin ,  Hyuntae Hwang ,  Changseok Lee ,  Seongin Yoon

IPC: H01L29/267 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/76

Abstract: Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.

公开(公告)号：US12211744B2

公开(公告)日：2025-01-28

申请号：US17552756

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook Shin ,  Hyeonjin Shin ,  Alum Jung ,  Changseok Lee

IPC: H01L21/768 ,  C01B32/186 ,  C23C16/02 ,  C23C16/26 ,  C23C16/505 ,  C23C16/511 ,  H01L21/285 ,  H01L23/532

Abstract: A method of forming nanocrystalline graphene according to an embodiment may include: arranging a substrate having a pattern in a reaction chamber; injecting a reaction gas into the reaction chamber, where the reaction gas includes a carbon source gas, an inert gas, and a hydrogen gas that are mixed; generating a plasma of the reaction gas in the reaction chamber; and directly growing the nanocrystalline graphene on a surface of the pattern using the plasma of the reaction gas at a process temperature. The pattern may include a first material and the substrate may include a second material different from the first material.

公开(公告)号：US12139814B2

公开(公告)日：2024-11-12

申请号：US18298692

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok Lee ,  Hyeonsuk Shin ,  Hyeonjin Shin ,  Seokmo Hong ,  Minhyun Lee ,  Seunggeol Nam ,  Kyungyeol Ma

IPC: C30B29/38 ,  H01L21/02

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

公开(公告)号：US12061312B2

公开(公告)日：2024-08-13

申请号：US17459537

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Choi ,  Hyeonjin Shin ,  Changseok Lee ,  Sangwon Kim

IPC: G02B1/113 ,  G02F1/1335 ,  G03F7/09 ,  H01L21/027 ,  H01L27/146 ,  H01L31/0216 ,  H01L31/052 ,  H10K50/86

CPC classification number: G02B1/113 ,  G03F7/091 ,  H01L21/0276 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L31/02168 ,  H01L31/052 ,  H10K50/86 ,  G02F1/133502

Abstract: Provided are an amorphous boron nitride film and an anti-reflection coating structure including the amorphous boron nitride film. The amorphous boron nitride film has an amorphous structure including an sp3 hybrid bond and an sp2 hybrid bond, in which a ratio of the sp3 hybrid bond in the amorphous boron nitride film is less than about 20%.

公开(公告)号：US11978704B2

公开(公告)日：2024-05-07

申请号：US16933544

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Hyeonjin Shin ,  Seongjun Park ,  Donghyun Im ,  Hyun Park ,  Keunwook Shin ,  Jongmyeong Lee ,  Hanjin Lim

IPC: H01L23/532

CPC classification number: H01L23/53276 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer.