公开(公告)号：US11812607B2

公开(公告)日：2023-11-07

申请号：US17685794

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmi Yoon ,  Donghyun Im ,  Jooyub Kim ,  Juhyung We ,  Namhoon Lee ,  Chunhyung Chung

IPC: H01L21/768 ,  H10B12/00 ,  H01L21/762 ,  H01L29/06

CPC classification number: H10B12/34 ,  H01L21/76224 ,  H01L21/76829 ,  H01L29/0653 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.

公开(公告)号：US11765885B2

公开(公告)日：2023-09-19

申请号：US17210931

申请日：2021-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyewon Kim ,  Juhyung We ,  Sungmi Yoon ,  Donghyun Im ,  Sangwoon Lee ,  Taiuk Rim ,  Kyosuk Chae

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78

CPC classification number: H10B12/34 ,  H01L21/28044 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/7834 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor device including a substrate including a recess; a gate insulation layer on a surface of the recess; a first gate pattern on the gate insulation layer and filling a lower portion of the recess; a second gate pattern on the first gate pattern in the recess and including a material having a work function different from a work function of the first gate pattern; a capping insulation pattern on the second gate pattern and filling an upper portion of the recess; a leakage blocking oxide layer on the gate insulation layer at an upper sidewall of the recess above an upper surface of the first gate pattern and contacting a sidewall of the capping insulation pattern; and impurity regions in the substrate and adjacent to the upper sidewall of the recess, each impurity region having a lower surface higher than the upper surface of the first gate pattern.

公开(公告)号：US11978704B2

公开(公告)日：2024-05-07

申请号：US16933544

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Hyeonjin Shin ,  Seongjun Park ,  Donghyun Im ,  Hyun Park ,  Keunwook Shin ,  Jongmyeong Lee ,  Hanjin Lim

IPC: H01L23/532

CPC classification number: H01L23/53276 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer.

公开(公告)号：US11296089B2

公开(公告)日：2022-04-05

申请号：US16850223

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmi Yoon ,  Donghyun Im ,  Jooyub Kim ,  Juhyung We ,  Namhoon Lee ,  Chunhyung Chung

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.

公开(公告)号：US11742401B2

公开(公告)日：2023-08-29

申请号：US17340667

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmi Yoon ,  Jooyub Kim ,  Daehyun Kim ,  Juhyung We ,  Donghyun Im ,  Chunhyung Chung

IPC: H01L29/423 ,  H01L29/49 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H01L29/49 ,  H10B12/053 ,  H10B12/34 ,  H10B12/488 ,  H10B12/30 ,  H10B12/315

Abstract: A semiconductor device may include a substrate including a recess, a gate insulation layer on a surface of the recess, an impurity barrier layer on a surface of the gate insulation layer to cover the surface of the gate insulation layer, a first gate pattern on impurity barrier layer to fill a lower portion of the recess, a second gate pattern on the first gate pattern in the recess, a capping insulation pattern on the second gate pattern to fill the recess, and impurity regions at the substrate adjacent to an upper sidewall of the recess. The impurity barrier layer may have a concentration of nitrogen higher than a concentration of nitrogen included in the gate insulation layer. The second gate pattern may include a material different from a material of the first gate pattern. A lower surface of the impurity regions may be higher than an upper surface of the first gate pattern. Thus, the semiconductor device may have good characteristics.

公开(公告)号：US20200350256A1

公开(公告)日：2020-11-05

申请号：US16933544

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Hyeonjin Shin ,  Seongjun Park ,  Donghyun Im ,  Hyun Park ,  Keunwook Shin ,  Jongmyeong Lee ,  Hanjin Lim

IPC: H01L23/532

Abstract: Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer.