公开(公告)号：US20230253042A1

公开(公告)日：2023-08-10

申请号：US18163590

申请日：2023-02-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji TANAKA ,  Yohei SAWADA ,  Masao MORIMOTO

IPC: G11C15/04 ,  G11C5/14

CPC classification number: G11C15/04 ,  G11C5/148

Abstract: A semiconductor device includes a memory array having a plurality of associative memory cells arranged in a matrix form for storing entries. The memory array is divided into a plurality of memory blocks for sequentially performing a retrieval operation along a column direction, and further includes a plurality of match lines corresponding to the respective memory blocks and provided correspondingly to each memory cell row, a plurality of search lines corresponding to the respective memory blocks and provided correspondingly to each memory cell column, and a plurality of match amplifiers corresponding to the respective memory blocks and provided to the plurality of match lines. The match line provided correspondingly to the preceding memory block is set to become shorter than the match line provided correspondingly to the subsequent memory block. The memory array further includes a timing control unit for controlling timing for driving the search line of the subsequent memory block based on a length of the match line provided correspondingly to the preceding memory block.

公开(公告)号：US20200075115A1

公开(公告)日：2020-03-05

申请号：US16540788

申请日：2019-08-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato YOKOYAMA ,  Shinji TANAKA

IPC: G11C29/18 ,  G11C7/22

Abstract: A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.

公开(公告)号：US20180261280A1

公开(公告)日：2018-09-13

申请号：US15981355

申请日：2018-05-16

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Makoto YABUUCHI ,  Yuta YOSHIDA

IPC: G11C11/419 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C7/08 ,  G11C11/418 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

公开(公告)号：US20180226135A1

公开(公告)日：2018-08-09

申请号：US15947075

申请日：2018-04-06

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Shunya NAGATA ,  Shinji TANAKA

IPC: G11C29/12 ,  G11C11/418 ,  G11C29/18 ,  G11C29/02 ,  G11C11/419 ,  G11C7/10 ,  G11C11/412 ,  G11C11/406 ,  G11C8/16 ,  G11C8/10

CPC classification number: G11C29/12 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/18 ,  G11C2029/1202

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

公开(公告)号：US20170263333A1

公开(公告)日：2017-09-14

申请号：US15606562

申请日：2017-05-26

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Shunya NAGATA ,  Shinji TANAKA

IPC: G11C29/12 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10

CPC classification number: G11C29/12 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/18 ,  G11C2029/1202

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

公开(公告)号：US20170092378A1

公开(公告)日：2017-03-30

申请号：US15234910

申请日：2016-08-11

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Yuichiro ISHll ,  Masaki TSUKUDE ,  Yoshikazu SAITO

IPC: G11C29/12 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C7/00 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/28 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Provided is a semiconductor memory device that is capable of accurately detecting a retention failure of a memory cell. The semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.

公开(公告)号：US20150279454A1

公开(公告)日：2015-10-01

申请号：US14658163

申请日：2015-03-14

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Abstract translation: 提供的半导体存储装置可以增加写入裕度并抑制芯片面积的增加。 半导体存储装置包括以矩阵形式布置的多个存储单元; 对应于存储器单元的每列布置的多个位线对; 写入驱动器电路，根据写入数据将数据发送到所选列的位线对; 以及将所选列的位线对的低电位侧的位线驱动到负电压电平的写辅助电路。 写辅助电路包括第一信号线; 第一驱动电路，其根据控制信号驱动第一信号布线; 以及第二信号布线，其通过与第一信号布线的线间耦合电容通过第一驱动电路的驱动而耦合到低电位侧的位线并产生负电压。

公开(公告)号：US20140313811A1

公开(公告)日：2014-10-23

申请号：US14321169

申请日：2014-07-01

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Makoto Yabuuchi ,  Yuta Yoshida

IPC: G11C5/06

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.