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    Semiconductor integrated circuit device
    21.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US09985038B2

    公开(公告)日：2018-05-29

    申请号：US15448585

    申请日：2017-03-02

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/417 ,  H01L29/49 ,  H01L29/78

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    Low power semiconductor memory device
    22.
    发明授权
    Low power semiconductor memory device 有权

    公开(公告)号：US09928900B2

    公开(公告)日：2018-03-27

    申请号：US15478237

    申请日：2017-04-03

    Applicant: Renesas Electronics Corporation

    Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

    IPC: G11C5/06 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

    Abstract: A semiconductor device having static memory cells is designed to reduce leakage current and power consumption. The static memory cells are coupled to word lines and bit lines, and the word lines are coupled to word drivers. A first P channel MOS transistor (MOS power switch) has a gate coupled to receive a first control signal, and a second P channel MOS transistor (MOS power switch) has a gate coupled to receive a second control signal different from the first control signal. Source-drain paths of the first and second P channel MOS transistors (MOS power switches) are coupled to respective voltage supply points for different parts of the semiconductor device, such as voltage supply points for the memory cells and the word drivers, or voltage supply points for a logic circuit and the word drivers.

    Semiconductor integrated circuit device
    23.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US09646678B2

    公开(公告)日：2017-05-09

    申请号：US15216327

    申请日：2016-07-21

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: G11C11/412 ,  H01L27/11 ,  G11C11/417

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    Semiconductor integrated circuit device
    26.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US09449678B2

    公开(公告)日：2016-09-20

    申请号：US14752514

    申请日：2015-06-26

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L29/76 ,  H01L27/11 ,  G11C11/412 ,  G11C11/417

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

    Abstract translation: 构成SRAM单元的逆变器的P型阱区域被细分成两部分，它们设置在N型阱区域NW1的相对侧上，并且形成为使得形成晶体管的扩散层具有 没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

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