公开(公告)号：US10229732B2

公开(公告)日：2019-03-12

申请号：US15876132

申请日：2018-01-20

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C5/06 ,  G11C11/419 ,  G11C5/14 ,  G11C11/417 ,  G11C11/412

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US20160071573A1

公开(公告)日：2016-03-10

申请号：US14940654

申请日：2015-11-13

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/417

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract translation: 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

公开(公告)号：US20160049188A1

公开(公告)日：2016-02-18

申请号：US14752514

申请日：2015-06-26

Applicant: Renesas Electronics Corporation

Inventor： Kenichi OSADA ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

IPC: G11C11/417

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

Abstract: A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

Abstract translation: 构成SRAM单元的逆变器的P型阱区域被细分成两部分，它们设置在N型阱区域NW1的相对侧上，并且形成为使得形成晶体管的扩散层具有 没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

公开(公告)号：US10573376B2

公开(公告)日：2020-02-25

申请号：US16271947

申请日：2019-02-11

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C5/06 ,  G11C11/419 ,  G11C5/14 ,  G11C11/417 ,  G11C11/412

Abstract: A logic circuit in a system LSI (Large Scale Integrated Circuit) is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM (Static Random Access Memory) circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US09984744B2

公开(公告)日：2018-05-29

申请号：US15680269

申请日：2017-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji Nii ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

IPC: G11C5/14 ,  G11C11/419 ,  G11C5/06 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

公开(公告)号：US20180144790A1

公开(公告)日：2018-05-24

申请号：US15876132

申请日：2018-01-20

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US09754659B2

公开(公告)日：2017-09-05

申请号：US14940654

申请日：2015-11-13

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/00 ,  G11C11/417 ,  G11C5/14 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US20140219010A1

公开(公告)日：2014-08-07

申请号：US14245124

申请日：2014-04-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/412

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract translation: 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

公开(公告)号：US08797791B2

公开(公告)日：2014-08-05

申请号：US13865279

申请日：2013-04-18

Applicant: Renesas Electronics Corporation

Inventor： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC: H01L29/788 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H03K19/00 ,  H01L27/092 ,  H01L27/11 ,  H01L27/105 ,  G11C11/412

CPC classification number: G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract translation: 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US20170206951A1

公开(公告)日：2017-07-20

申请号：US15478237

申请日：2017-04-03

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.