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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    半导体集成电路设备

    公开(公告)号：US20160049188A1

    公开(公告)日：2016-02-18

    申请号：US14752514

    申请日：2015-06-26

    Applicant: Renesas Electronics Corporation

    Inventor： Kenichi OSADA ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: G11C11/417

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

    Abstract translation: 构成SRAM单元的逆变器的P型阱区域被细分成两部分，它们设置在N型阱区域NW1的相对侧上，并且形成为使得形成晶体管的扩散层具有 没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20150049541A1

    公开(公告)日：2015-02-19

    申请号：US14484998

    申请日：2014-09-12

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Masanao YAMAOKA ,  Kenichi OSADA ,  Kazumasa YANAGISAWA

    IPC: G11C11/417 ,  G11C5/14

    CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C5/148

    Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

    Abstract translation: 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, POWER SUPPLY DEVICE, AND METHOD OF CONTROLLING POWER SUPPLY DEVICE
    7.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, POWER SUPPLY DEVICE, AND METHOD OF CONTROLLING POWER SUPPLY DEVICE 有权
    半导体集成电路装置，电源装置及控制电源装置的方法

    公开(公告)号：US20130278059A1

    公开(公告)日：2013-10-24

    申请号：US13862803

    申请日：2013-04-15

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Ming LIU ,  Tatsuo NAKAGAWA ,  Kenichi OSADA

    IPC: G05F1/577 ,  G05F1/46

    CPC classification number: H02M1/088 ,  G01R19/10 ,  G05F1/46 ,  G05F1/577 ,  H02M3/157 ,  H02M3/158 ,  H02M2001/0025 ,  H03M1/12 ,  Y10T307/406

    Abstract: A conventional power supply device has a problem in miniaturization. A power supply device generates a prediction value of an error signal from first and second error signals, and controls an output voltage so that the prediction value lies between first and second threshold values. The first error signal is obtained by converting an error voltage based on the difference between the output voltage and a reference voltage at a first timing. The second error signal is obtained by converting an error voltage based on the difference between the output voltage and the reference voltage at a second timing.

    Abstract translation: 传统的电源装置在小型化方面存在问题。 电源装置从第一和第二误差信号产生误差信号的预测值，并且控制输出电压，使得预测值位于第一和第二阈值之间。 第一误差信号是通过基于第一定时处的输出电压和参考电压之差的误差电压来获得的。 通过在第二定时将基于输出电压和参考电压之间的差的误差电压转换来获得第二误差信号。

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180158511A1

    公开(公告)日：2018-06-07

    申请号：US15887190

    申请日：2018-02-02

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Masanao YAMAOKA ,  Kenichi OSADA ,  Kazumasa YANAGISAWA

    IPC: G11C11/417 ,  G11C5/14

    CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C5/148

    Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

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