公开(公告)号：US20150357026A1

公开(公告)日：2015-12-10

申请号：US14826911

申请日：2015-08-14

Applicant: Renesas Electronics Corporation

Inventor： Kenichi OSADA ,  Koichiro ISHIBASHI ,  Yoshikazu SAITOH ,  Akio NISHIDA ,  Masaru NAKAMICHI ,  Naoki KITAI

IPC: G11C11/412 ,  G11C11/418 ,  H01L27/11

CPC classification number: G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract translation: 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US20150155031A1

公开(公告)日：2015-06-04

申请号：US14323064

申请日：2014-07-03

Applicant: Renesas Electronics Corporation

Inventor： Kenichi OSADA ,  Koichiro ISHIBASHI ,  Yoshikazu SAITOH ,  Akio NISHIDA ,  Masaru NAKAMICHI ,  Naoki KITAI

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract translation: 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US20140126278A1

公开(公告)日：2014-05-08

申请号：US14151581

申请日：2014-01-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US20150220095A1

公开(公告)日：2015-08-06

申请号：US14684889

申请日：2015-04-13

Applicant: Renesas Electronics Corporation

Inventor： Masafumi ONOUCHI ,  Kazuo OTSUGA ,  Yasuto IGARASHI ,  Sadayuki MORITA ,  Koichiro ISHIBASHI ,  Kazumasa YANAGISAWA

IPC: G05F1/59

CPC classification number: G05F1/59 ,  G06F1/26 ,  H01L23/5286 ,  H01L2924/0002 ,  H02M2001/0045 ,  H03K17/102 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract translation: 半导体集成电路包括多个输出晶体管，每个输出晶体管根据施加到控制端子的阻抗控制信号所指示的控制值来控制输出电压的大小相对于负载电流的大小，输出输出的电压监视电路 表示输出电压的电压值的电压监视值，以及根据表示输出电压的目标值的基准电压与输出电压监视值之间的误差值的大小来控制控制值的大小的控制电路， 并且基于控制值来控制是否任何这种晶体管进入导通状态。 控制电路根据预先通知负载电流变化的预通知信号，在预定期间内增加控制值相对于误差值的变化步长。

公开(公告)号：US20180247692A1

公开(公告)日：2018-08-30

申请号：US15964864

申请日：2018-04-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419 ,  G11C5/06 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

公开(公告)号：US20170345488A1

公开(公告)日：2017-11-30

申请号：US15680269

申请日：2017-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419 ,  G11C11/412 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

公开(公告)号：US20170011794A1

公开(公告)日：2017-01-12

申请号：US15274852

申请日：2016-09-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US20160078925A1

公开(公告)日：2016-03-17

申请号：US14942822

申请日：2015-11-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。