公开(公告)号：US20130135036A1

公开(公告)日：2013-05-30

申请号：US13748663

申请日：2013-01-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuki FUKUOKA ,  Yasuto IGARASHI ,  Ryo MORI ,  Yoshihiko YASU ,  Toshio SASAKI

IPC: H03K5/00

CPC classification number: H03K5/00 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/11807 ,  H03K3/00 ,  H03K19/0016

Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.

Abstract translation: 通过使用电源开关控制和DVFS技术组合实现断电电路技术实现功耗的有效降低，实现低功耗。 在半导体基板上形成的DEEP-NWELL区域中，形成供给电源电压的电源开关部，由电源开关部进行电源切断的电路块和电平移位器。 供给另一电源电压的另一个电源开关部分，由电源开关部分执行电源切断的电路块和电平移位器形成在形成在半导体衬底上的另一个DEEP-NWELL区域中。 在这种布置中，不存在通过半导体衬底上形成的每个DEEP-NWELL区域在不同电源之间短路的可能性。

公开(公告)号：US20150220095A1

公开(公告)日：2015-08-06

申请号：US14684889

申请日：2015-04-13

Applicant: Renesas Electronics Corporation

Inventor： Masafumi ONOUCHI ,  Kazuo OTSUGA ,  Yasuto IGARASHI ,  Sadayuki MORITA ,  Koichiro ISHIBASHI ,  Kazumasa YANAGISAWA

IPC: G05F1/59

CPC classification number: G05F1/59 ,  G06F1/26 ,  H01L23/5286 ,  H01L2924/0002 ,  H02M2001/0045 ,  H03K17/102 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract translation: 半导体集成电路包括多个输出晶体管，每个输出晶体管根据施加到控制端子的阻抗控制信号所指示的控制值来控制输出电压的大小相对于负载电流的大小，输出输出的电压监视电路 表示输出电压的电压值的电压监视值，以及根据表示输出电压的目标值的基准电压与输出电压监视值之间的误差值的大小来控制控制值的大小的控制电路， 并且基于控制值来控制是否任何这种晶体管进入导通状态。 控制电路根据预先通知负载电流变化的预通知信号，在预定期间内增加控制值相对于误差值的变化步长。