公开(公告)号：US20130135036A1

公开(公告)日：2013-05-30

申请号：US13748663

申请日：2013-01-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuki FUKUOKA ,  Yasuto IGARASHI ,  Ryo MORI ,  Yoshihiko YASU ,  Toshio SASAKI

IPC: H03K5/00

CPC classification number: H03K5/00 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/11807 ,  H03K3/00 ,  H03K19/0016

Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.

Abstract translation: 通过使用电源开关控制和DVFS技术组合实现断电电路技术实现功耗的有效降低，实现低功耗。 在半导体基板上形成的DEEP-NWELL区域中，形成供给电源电压的电源开关部，由电源开关部进行电源切断的电路块和电平移位器。 供给另一电源电压的另一个电源开关部分，由电源开关部分执行电源切断的电路块和电平移位器形成在形成在半导体衬底上的另一个DEEP-NWELL区域中。 在这种布置中，不存在通过半导体衬底上形成的每个DEEP-NWELL区域在不同电源之间短路的可能性。

公开(公告)号：US20170075404A1

公开(公告)日：2017-03-16

申请号：US15224380

申请日：2016-07-29

Applicant: Renesas Electronics Corporation

Inventor： Yuko KITAJI ,  Kazuki FUKUOKA ,  Ryo MORI ,  Toshifumi UEMURA

IPC: G06F1/32

CPC classification number: G06F1/305 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3237

Abstract: There is provided a semiconductor device that can follow a fast voltage change such as a large voltage drop occurring at the time of rapid load fluctuation. The semiconductor device includes a voltage sensor which monitors a power supply voltage at a sampling speed higher than the assumed frequency of power supply voltage fluctuation and outputs a voltage code value, a voltage drop determination circuit which determines, from the voltage code value, that a voltage drop causing a malfunction of a system occurs, and outputs a clock stop signal, and a clock control circuit which controls clock stop, restart, and frequency change.

Abstract translation: 提供了可以跟随快速电压变化的半导体器件，例如在快速负载波动时发生的大的电压降。 半导体装置包括：电压传感器，其以比假想电源电压波动的频率高的采样速度监视电源电压，并输出电压代码值;电压降判定电路，根据电压代码值确定： 产生导致系统故障的电压降，并输出时钟停止信号，以及控制时钟停止，重启和频率变化的时钟控制电路。

公开(公告)号：US20210365093A1

公开(公告)日：2021-11-25

申请号：US17319880

申请日：2021-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryo MORI ,  Kazuki FUKUOKA ,  Kenichi SHIMADA

IPC: G06F1/26 ,  G06F1/28

Abstract: A semiconductor device includes: a plurality of cores configured to receive power from a power supply; a plurality of power switch circuits provided for each core and configured to control the power supplied to the corresponding cores; a compare circuit configured to receive power from the power supply and compare output data of the plurality of cores; and a core voltage monitor circuit configured to monitor a voltage of a node that connects the power supply and the compare circuit.

公开(公告)号：US20160064063A1

公开(公告)日：2016-03-03

申请号：US14817777

申请日：2015-08-04

Applicant: Renesas Electronics Corporation

Inventor： Takao NOMURA ,  Ryo MORI ,  Kazuki FUKUOKA

IPC: G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40626 ,  G11C11/40618 ,  G11C11/4074 ,  G11C2211/4068 ,  H01L2224/16145 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device capable of controlling a memory while preventing the functional deterioration of the memory and reducing the power consumption of the semiconductor device is provided. The semiconductor device includes a first semiconductor chip (logic chip) and a second semiconductor chip (memory chip). The first semiconductor chip includes a plurality of temperature sensors disposed in mutually different places, and a memory controller that controls each of a plurality of memory areas provided in the second semiconductor chip based on output results of a respective one of the plurality of temperature sensors.

Abstract translation: 提供一种能够在防止存储器的功能劣化并降低半导体器件的功耗的同时控制存储器的半导体器件。 半导体器件包括第一半导体芯片（逻辑芯片）和第二半导体芯片（存储芯片）。 第一半导体芯片包括设置在相互不同的位置的多个温度传感器，以及存储器控制器，其基于多个温度传感器中的相应一个的输出结果来控制设置在第二半导体芯片中的多个存储区域中的每一个。