公开(公告)号：US20180286885A1

公开(公告)日：2018-10-04

申请号：US16000967

申请日：2018-06-06

Applicant: Renesas Electronics Corporation

Inventor： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Yoshihiko YASU ,  Kenji HIROSE ,  Takahiro IRITA

IPC: H01L27/118 ,  H03K3/03 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H03K17/16 ,  H03K3/037 ,  H01L27/02 ,  G06F17/50 ,  H01L23/528 ,  H01L27/00 ,  H01L29/78

CPC classification number: H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H03K19/0008 ,  H03K19/00346 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

公开(公告)号：US20160365358A1

公开(公告)日：2016-12-15

申请号：US15246796

申请日：2016-08-25

Applicant: Renesas Electronics Corporation

Inventor： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Yoshihiko YASU ,  Kenji HIROSE ,  Takahiro IRITA

IPC: H01L27/118 ,  H03K17/16 ,  G11C11/419 ,  H03K3/03

CPC classification number: H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

公开(公告)号：US20130228939A1

公开(公告)日：2013-09-05

申请号：US13865662

申请日：2013-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Yoshihiko YASU ,  Kenji HIROSE ,  Takahiro IRITA

IPC: H01L23/48

CPC classification number: H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

公开(公告)号：US20130135036A1

公开(公告)日：2013-05-30

申请号：US13748663

申请日：2013-01-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuki FUKUOKA ,  Yasuto IGARASHI ,  Ryo MORI ,  Yoshihiko YASU ,  Toshio SASAKI

IPC: H03K5/00

CPC classification number: H03K5/00 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/11807 ,  H03K3/00 ,  H03K19/0016

Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.

Abstract translation: 通过使用电源开关控制和DVFS技术组合实现断电电路技术实现功耗的有效降低，实现低功耗。 在半导体基板上形成的DEEP-NWELL区域中，形成供给电源电压的电源开关部，由电源开关部进行电源切断的电路块和电平移位器。 供给另一电源电压的另一个电源开关部分，由电源开关部分执行电源切断的电路块和电平移位器形成在形成在半导体衬底上的另一个DEEP-NWELL区域中。 在这种布置中，不存在通过半导体衬底上形成的每个DEEP-NWELL区域在不同电源之间短路的可能性。

公开(公告)号：US20140167819A1

公开(公告)日：2014-06-19

申请号：US14187030

申请日：2014-02-21

Applicant: Renesas Electronics Corporation

Inventor： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Yoshihiko YASU ,  Kenji HIROSE ,  Takahiro IRITA

IPC: H03K3/037

CPC classification number: H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract translation: 一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。 在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。 还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。

公开(公告)号：US20200006384A1

公开(公告)日：2020-01-02

申请号：US16565765

申请日：2019-09-10

Applicant: Renesas Electronics Corporation

Inventor： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Yoshihiko YASU ,  Kenji HIROSE ,  Takahiro IRITA

IPC: H01L27/118 ,  H01L23/528 ,  H01L23/50 ,  H01L23/48 ,  H03K3/03 ,  H03K3/037 ,  G11C11/419 ,  H03K17/16 ,  H01L27/02 ,  G06F17/50

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

公开(公告)号：US20150295572A1

公开(公告)日：2015-10-15

申请号：US14746920

申请日：2015-06-23

Applicant: Renesas Electronics Corporation

Inventor： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Yoshihiko YASU ,  Kenji HIROSE ,  Takahiro IRITA

IPC: H03K17/16 ,  H01L27/02 ,  H01L23/528 ,  H01L23/50

CPC classification number: H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract translation: 一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。 在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。 还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。