公开(公告)号：US20220131013A1

公开(公告)日：2022-04-28

申请号：US17077807

申请日：2020-10-22

Applicant: QUALCOMM Incorporated

Inventor： Chenjie TANG ,  Gengming TAO ,  Ye LU ,  Bin YANG ,  Xia LI

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device implemented with multiple channels in a gate-all-around (GAA) high-electron-mobility transistor (HEMT) and techniques for fabricating such a device. One example semiconductor device generally includes a substrate; a first gate layer disposed above the substrate; a first barrier layer disposed above the first gate layer; a first channel region disposed above the first barrier layer; a second barrier layer disposed above the first channel region; a second gate layer disposed above the second barrier layer; a third barrier layer disposed above the second gate layer; a second channel region disposed above the third barrier layer; a fourth barrier layer disposed above the second channel region; a source region; and a drain region.

公开(公告)号：US20210351276A1

公开(公告)日：2021-11-11

申请号：US16868376

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Peijie FENG ,  Chenjie TANG

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66

Abstract: An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

公开(公告)号：US20200051718A1

公开(公告)日：2020-02-13

申请号：US16058928

申请日：2018-08-08

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Chao SONG ,  Ye LU

IPC: H01C3/02 ,  H01L49/02 ,  H01L27/02 ,  G06F17/50 ,  H01C3/16 ,  H01C17/04

Abstract: A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.

公开(公告)号：US20200044013A1

公开(公告)日：2020-02-06

申请号：US16053124

申请日：2018-08-02

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Haitao CHENG ,  Chao SONG

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/283 ,  H01L21/311

Abstract: A capacitor includes a first conductive element having a plurality of first conductive fingers and a second conductive element having a plurality of second conductive fingers. The first conductive fingers are interdigitated with the second conductive fingers. The capacitor further includes a conformally deposited dielectric material that separates the plurality of first conductive fingers from the plurality of second conductive fingers.

公开(公告)号：US20200020795A1

公开(公告)日：2020-01-16

申请号：US16033597

申请日：2018-07-12

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Haining YANG ,  Hyeokjin LIM

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/321

Abstract: A semiconductor device includes a substrate, a gate region formed on the substrate, a self-aligned gate cut formed in the gate region, and a middle of line (MOL) area formed on the gate region, wherein the self-aligned gate cut provides critical dimensions in a range from 5 nm to 30 nm. The self-aligned gate cut reduces capacitance and power, provides flexibility in placement of the MOL area, and reduces local routing congestion.

公开(公告)号：US20190103320A1

公开(公告)日：2019-04-04

申请号：US15723224

申请日：2017-10-03

Applicant: QUALCOMM Incorporated

Inventor： Lixin GE ,  Bin YANG ,  Ye LU ,  Junjing BAO ,  Periannan CHIDAMBARAM

IPC: H01L21/8234 ,  H01L27/06 ,  H01L23/522

Abstract: Middle-of-line (MOL) shielded gate in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC to reduce gate to drain parasitic capacitance in the semiconductor area. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized close to semiconductor devices to more effectively reduce parasitic capacitance of the semiconductor devices without adding costs or defects to the current fabrication processes. The current fabrication processes may be used to create contacts in the MOL to fabricate the metal resistor.

公开(公告)号：US20190027554A1

公开(公告)日：2019-01-24

申请号：US15816295

申请日：2017-11-17

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Yun YUE ,  Phanikumar KONKAPAKA ,  Bin YANG ,  Chuan-Hsing CHEN

IPC: H01L29/06 ,  H01L23/522

Abstract: A metal-oxide-semiconductor (MOS) device for radio frequency (RF) applications may include a guard ring. The guard ring may surround the MOS device and at least one other MOS device. The MOS device may further include a level zero contact layer coupled to a first interconnect layer through level zero interconnects and vias. The first interconnect layer may be for routing to the MOS device.

公开(公告)号：US20180366413A1

公开(公告)日：2018-12-20

申请号：US15687362

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Bin YANG ,  Junjing BAO

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  C01B32/182 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02362 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823493 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L29/78 ,  H01L29/7851

Abstract: An integrated circuit may include multiple back-end-of-line (BEOL) interconnect layers. The BEOL interconnect layers may include conductive lines and conductive vias. The integrated circuit may further include an interlayer dielectric (ILD) between the BEOL interconnect layers. The ILD may include the conductive lines and the conductive vias. At least a portion of the ILD may include a low-K insulating graphene alloy.

公开(公告)号：US20180342585A1

公开(公告)日：2018-11-29

申请号：US15672017

申请日：2017-08-08

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L29/72

CPC classification number: H01L29/1606 ,  H01L21/02115 ,  H01L21/02181 ,  H01L21/02271 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66068 ,  H01L29/6656 ,  H01L29/72 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20210343830A1

公开(公告)日：2021-11-04

申请号：US16866316

申请日：2020-05-04

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Ye LU ,  Junjing BAO

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768

Abstract: Certain aspects of the present disclosure generally relate to a metal-oxide-metal (MOM) capacitor formed from a subtractive back-end-of-line (BEOL) scheme. One example method of fabricating a semiconductor device generally includes forming an active layer and forming a capacitive element above the active layer with a back-end-of-line subtractive process for conductive materials.