公开(公告)号：US10141306B2

公开(公告)日：2018-11-27

申请号：US15418651

申请日：2017-01-27

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/3115 ,  H01L27/088 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66

Abstract: To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

公开(公告)号：US20170317167A1

公开(公告)日：2017-11-02

申请号：US15650042

申请日：2017-07-14

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02282 ,  H01L21/762 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay. Also, by use of low-K dielectric material in only selected, localized areas of ILD material of selected circuits, mechanical and/or thermal stability concern issues that would arise from use of low-K dielectric material in all of the ILD material in the IC are avoided.

公开(公告)号：US20170309611A1

公开(公告)日：2017-10-26

申请号：US15133377

申请日：2016-04-20

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Junjing Bao

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66128 ,  H01L29/66545 ,  H01L29/8611

Abstract: Aspects for forming a self-aligned single diffusion break (SDB) isolation structure in a gate region of a diode for reduced capacitance, resistance, and/or area are disclosed. In one aspect, a diode is provided that includes a semiconductor substrate having a well region. P-doped and N-doped diffusion regions are formed in the well region of the semiconductor substrate. A self-aligned SDB isolation structure is formed in and self-aligned with a gate region between the P-doped and N-doped diffusion regions that electrically isolates such regions. The self-aligned SDB isolation structure reduces the parasitic capacitance of the diode compared to diodes having conductive gate structures in the gate region. The self-aligned SDB isolation structure has a width that reduces the length of a discharge path compared to conventional diodes, which reduces on-state resistance of the diode.

公开(公告)号：US09773866B2

公开(公告)日：2017-09-26

申请号：US14743143

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L29/06 ,  H01L23/532 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L29/0649 ,  H01L21/02282 ,  H01L21/762 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay. Also, by use of low-K dielectric material in only selected, localized areas of ILD material of selected circuits, mechanical and/or thermal stability concern issues that would arise from use of low-K dielectric material in all of the ILD material in the IC are avoided.

公开(公告)号：US09698232B2

公开(公告)日：2017-07-04

申请号：US14661953

申请日：2015-03-18

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Stanley Seungchul Song

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4958 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/32133 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/53238 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66568 ,  H01L29/78

Abstract: A semiconductor device includes a gate region, a conductive cap, and an interconnect. The gate region (e.g., a metal-gate transistor) includes a metal gate region and a high dielectric constant (high-K) gate dielectric region. The conductive cap is disposed on a surface of the metal gate region and on a surface of the high-K gate dielectric region, and the interconnect is disposed on the conductive cap. The conductive cap includes a conductive material that electrically connects the gate region to the interconnect.

公开(公告)号：US09633996B1

公开(公告)日：2017-04-25

申请号：US15081396

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： Lixin Ge ,  P R Chidambaram ,  Haining Yang ,  John Jianhong Zhu ,  Kern Rim

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L49/02 ,  H01L29/94 ,  H01L29/66 ,  H01L27/07

CPC classification number: H01L27/0629 ,  H01L27/0716 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/24 ,  H01L29/0653 ,  H01L29/66181 ,  H01L29/7851 ,  H01L29/94

Abstract: A semiconductor device arranged between a source voltage (Vss) and a power voltage (Vdd) may include a first terminal coupled to the power voltage Vdd. The semiconductor device may also include a decoupling capacitor. The decoupling capacitor may include a semiconductor fin coupled to the first terminal, a dielectric layer on the semiconductor fin, and a gate on the dielectric layer. The semiconductor device may further include a second terminal. The second terminal may include a conductive gate resistor coupled in series with the gate of the decoupling capacitor. The second terminal may be coupled to the source voltage Vss via a first interconnect layer (M1).

公开(公告)号：US09537007B2

公开(公告)日：2017-01-03

申请号：US14680711

申请日：2015-04-07

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Yanxiang Liu

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7845 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle the fin in the channel region. The gate-stressor member has a configuration that includes a partial cut spaced from the fin by a cut distance. The configuration causes, through the gate surfaces, a transverse stress in the fin, having a magnitude that corresponds to the cut distance. Transverse stressor members, formed of a metal, straddle the fin at regions outside of the channel region and cause, at the regions outside of the channel region, additional transverse stresses in the fin. The magnitude that corresponds to the cut distance, in combination with the additional transverse stresses, induces a longitudinal compressive strain in the channel region.

Abstract translation: 半导体鳍片包括沟道区域。 由金属形成的闸应力部件横向于翅片延伸并且包括在通道区域中跨过翅片的门表面。 闸门应力器构件具有包括与翅片间隔开切割距离的部分切割的构造。 该结构通过栅极表面导致鳍中的横向应力，其具有对应于切割距离的大小。 由金属形成的横向应力器构件在通道区域外的区域跨越翅片，并且在通道区域外的区域处引起翅片中额外的横向应力。 对应于切割距离的大小与附加的横向应力相结合，在通道区域中引起纵向压缩应变。

公开(公告)号：US20160372544A1

公开(公告)日：2016-12-22

申请号：US14743143

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L29/06 ,  H01L23/522 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L29/0649 ,  H01L21/02282 ,  H01L21/762 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay. Also, by use of low-K dielectric material in only selected, localized areas of ILD material of selected circuits, mechanical and/or thermal stability concern issues that would arise from use of low-K dielectric material in all of the ILD material in the IC are avoided.

Abstract translation: 公开了在层间电介质（ILD）材料中采用局部低介电常数（低K）材料的半导体集成电路（IC），以提高速度性能。 为了加快IC中所选择的电路的性能，否则会降低IC的整体速度性能，在IC制造过程中采用低K电介质材料。 低K电介质材料设置在其中设置选择电路的ILD材料的选定的局部区域中。 以这种方式，由于设置在低K ILD材料中的所选择的电路的电路元件和/或电路元件互连将经历减小的信号延迟，所以IC将在操作期间经历总体增加的速度性能。 此外，通过仅在所选电路的ILD材料的选定的局部区域中使用低K电介质材料，机械和/或热稳定性涉及由于在所有ILD材料中使用低K电介质材料而引起的问题 IC被避免。

公开(公告)号：US11687766B2

公开(公告)日：2023-06-27

申请号：US16012451

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Periannan Chidambaram

IPC: G06N3/065 ,  G06N3/084 ,  G11C11/54

CPC classification number: G06N3/065 ,  G06N3/084 ,  G11C11/54

Abstract: Methods, systems, and devices for an artificial neural network are described. In one example, an artificial neuron in an artificial neural network may include a resistor coupled with an input line and configured to indicate a synaptic weight and a fuse coupled with the resistor. The artificial neuron may also include a selection component coupled with the fuse and configured to activate the fuse for programming the resistor, and a second selection component coupled with the resistor and an output line, the second selection component configured to select the resistor for a read operation.

公开(公告)号：US20230009977A1

公开(公告)日：2023-01-12

申请号：US17371701

申请日：2021-07-09

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Haining Yang ,  Youseok Suh

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

Abstract: Source/drain contacts between transistor gates with abbreviated inner spacers for improved contact area are disclosed. Related methods of fabricating source/drain contacts and abbreviated inner spacers are also disclosed. Inner spacers formed on sidewalls of the gates of adjacent transistors are abbreviated to reduce an amount of the space the inner spacers occupy on the source/drain region, increasing a critical dimension of the source/drain contact. Abbreviated inner spacers extend from a top of the gate over a portion of the sidewalls to provide leakage current protection but do not fully extend to the semiconductor substrate. As a result, the critical dimension of the source/drain contact can extend from a sidewall on a first gate to a sidewall on a second gate. A source/drain contact formed between gates with abbreviated inner spacers has a greater surface area in contact with the source/drain region providing decreased contact resistance.