公开(公告)号：US20190035945A1

公开(公告)日：2019-01-31

申请号：US15659718

申请日：2017-07-26

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Gengming TAO

IPC: H01L29/94 ,  H01L29/06

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor offering at least two types of capacitance tuning, as well as techniques for fabricating the same. For example, a CMOS-compatible silicon on insulator (SOI) process with a buried oxide (BOX) layer may provide a transcap with a front gate (above the BOX layer) and a back gate (beneath the BOX layer). The front gate may offer lower voltage, coarse capacitance tuning, whereas the back gate may offer higher voltage, fine capacitance tuning. By offering both types of capacitance tuning, such transcaps may provide greater capacitance resolution. Several variations of transcaps with front gate and back gate tuning are illustrated and described herein.

公开(公告)号：US20180337242A1

公开(公告)日：2018-11-22

申请号：US15685877

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Xia LI ,  Gengming TAO ,  Periannan CHIDAMBARAM

IPC: H01L29/423 ,  H01L29/66

CPC classification number: H01L29/4238 ,  H01L29/2003 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/7786

Abstract: A compound semiconductor field effect transistor (FET) may include gallium nitride (GaN) and alloy material layers. The compound semiconductor FET may also include a pair of L-shaped contacts on the GaN and alloy material layers. The compound semiconductor FET may also include a pair of gate spacers between the L-shaped contacts and on the GaN and alloy material layers, each of the pair of gate spacers contacting one of the L-shaped contacts. The compound semiconductor FET may further include a base gate between the pair of gate spacers and on the GaN and alloy material layers, in which the pair of L-shaped contacts are self-aligned with the base gate.

公开(公告)号：US20180277671A1

公开(公告)日：2018-09-27

申请号：US15643815

申请日：2017-07-07

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Gengming TAO ,  Xia LI ,  Periannan CHIDAMBARAM

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66

Abstract: A compound semiconductor transistor may include a channel layer. The compound semiconductor transistor may also include a dielectric layer on the channel layer. The compound semiconductor transistor may further include a gate. The gate may include a vertical base portion through the dielectric layer and electrically contacting the channel layer. The gate may also include a head portion on the dielectric layer and electrically coupled to the vertical base portion of the gate.

公开(公告)号：US20160308062A1

公开(公告)日：2016-10-20

申请号：US15194125

申请日：2016-06-27

Applicant: QUALCOMM INCORPORATED

Inventor： Xia LI ,  Bin YANG ,  Seung Hyuk KANG

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7883 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/788 ,  H01L29/7881

Abstract: A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film.

公开(公告)号：US20240055429A1

公开(公告)日：2024-02-15

申请号：US17818933

申请日：2022-08-10

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/76 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/7606 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02568 ,  H01L21/8256 ,  H01L29/66969 ,  H03K19/20

Abstract: Disclosed is a complementary field effect transistor (CFET) formed from stacked 2D-material transistors. The 2D-material transistors are formed from transition metal dichalcogenide (TMD), which are atomically thin semiconductors. The stacked TMD transistors allow for enhanced drive current and lower switching capacitance, both of which are desirable.

公开(公告)号：US20230008615A1

公开(公告)日：2023-01-12

申请号：US17369532

申请日：2021-07-07

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Junjing BAO

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/24 ,  H01L27/092 ,  H01L29/66

Abstract: Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

公开(公告)号：US20220173039A1

公开(公告)日：2022-06-02

申请号：US17107078

申请日：2020-11-30

Applicant: QUALCOMM Incorporated

Inventor： Bin YANG ,  Haining YANG ,  Xia LI

IPC: H01L23/528 ,  H01L23/50 ,  H01L27/092 ,  H01L27/118

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with a buried power rail (BPR) having decreased resistance and a method of fabricating such a semiconductor device with a BPR. An example semiconductor device generally includes a substrate, a first transistor structure disposed above the substrate, a second transistor structure disposed above the substrate, and a BPR structure disposed between the first transistor structure and the second transistor structure. The BPR structure generally includes at least two distinguishable portions, which may be a first portion disposed above a second portion, the second portion having a greater width than the first portion.

公开(公告)号：US20210305250A1

公开(公告)日：2021-09-30

申请号：US16828487

申请日：2020-03-24

Applicant: QUALCOMM Incorporated

Inventor： Haining YANG ,  Xia LI ,  Bin YANG

IPC: H01L27/092 ,  H01L29/40 ,  H01L21/8238

Abstract: An integrated device that includes a substrate, a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled to only the gate.

公开(公告)号：US20210273409A1

公开(公告)日：2021-09-02

申请号：US16803668

申请日：2020-02-27

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Bin YANG ,  Xia LI

IPC: H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/343

Abstract: A distributed feedback (DFB) laser that includes a substrate comprising a first surface and a second surface, wherein the substrate comprises silicon; a plurality of shallow trench isolations (STIs) located over the second surface of the substrate; a grating region located over the plurality of STIs and the substrate, wherein the grating region comprises a III-V semiconductor material; a non-intentional doping (NID) region located over the grating region; and a contact region located over the NID region.

公开(公告)号：US20210020790A1

公开(公告)日：2021-01-21

申请号：US16511093

申请日：2019-07-15

Applicant: QUALCOMM Incorporated

Inventor： Gengming TAO ,  Xia LI ,  Bin YANG

IPC: H01L29/93 ,  H01L29/778 ,  H01L29/66

Abstract: Aspects generally relate to a P-N junction varactor that can be integrated with high electron mobility transistor (HEMT) in a single device or die. The varactor and HEMT are fabricated with the same materials forming various layers of the varactor and HEMT. Using the same material stack-up to form the varactor and HEMT can reduce the number of processing steps during the fabrication of the integrated varactor and HEMT device. The integrated varactor and HEMT device may be used for RF circuits, such as radio frequency front end (RFFE) devices for use in 5G.