公开(公告)号：US09251883B2

公开(公告)日：2016-02-02

申请号：US14498376

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Kendrick Hoy Leong Yuen ,  Karim Arabi

IPC: G11C11/18 ,  G11C11/16 ,  G11C14/00 ,  H03K19/18 ,  H03K3/356 ,  H03K3/59 ,  H03K3/3562

CPC classification number: G11C11/1693 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  G11C14/0081 ,  H03K3/356008 ,  H03K3/35625 ,  H03K3/59 ,  H03K19/18

Abstract: Systems and methods are directed to a single-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure, the dual GSHE-MTJ structure comprising a first GSHE-MTJ and a second GSHE-MTJ coupled between a first combined terminal and a second combined terminal, and a slave stage formed from a first inverter coupled to a second inverter. During a single clock cycle of a clock, a first data value is read out from the slave stage when a clock is in a high state and a second data value is written into the master stage, when the clock is in a low state. The first and second inverters are cross coupled in a latch configuration to hold the first data value as an output, when the clock is in the low state.

Abstract translation: 系统和方法涉及单相非易失性触发器（NVFF），其包括由双巨型旋转霍尔效应（GSHE） - 磁性隧道结（MTJ）结构形成的主级，双GSHE-MTJ 包括耦合在第一组合终端和第二组合终端之间的第一GSHE-MTJ和第二GSHE-MTJ的结构，以及由耦合到第二逆变器的第一逆变器形成的从级。 在时钟的单个时钟周期中，当时钟处于低状态时，当时钟处于高状态并且第二数据值被写入主站时，从从站读出第一数据值。 当时钟处于低电平状态时，第一和第二反相器以锁存配置交叉耦合以将第一数据值保持为输出。

公开(公告)号：US20150145576A1

公开(公告)日：2015-05-28

申请号：US14331688

申请日：2014-07-15

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Raghu Sagar Madala ,  Kendrick Hoy Leong Yuen ,  Karim Arabi ,  Robert Philip Gilmore

IPC: H03K3/45 ,  H03K19/20 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/45 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  H01L43/08 ,  H03K19/18 ,  H03K19/20

Abstract: Aspects described herein are related to pipeline circuits employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) for performing logical operations. In one aspect, a pipeline circuit is disclosed. The pipeline circuit includes a first pipeline stage and a second pipeline stage. The first pipeline stage is configured to store a first bit set and to generate a first charge current representing the first bit set. The second pipeline stage includes a first GSHE MTJ element. The first GSHE MTJ element is configured to set a first bit state for the first logical operation, and has a first threshold current level. The first GSHE MTJ element is configured to generate a first GSHE spin current in response to the first charge current. In this manner, the first GSHE MTJ element is also configured to perform the first logical operation on the first bit set.

Abstract translation: 本文描述的方面涉及采用用于执行逻辑操作的巨型旋转霍尔效应（GSHE）磁性隧道结（MTJ）元件的流水线电路。 一方面，公开了一种流水线电路。 管线电路包括第一流水线阶段和第二流水线阶段。 第一流水线级被配置为存储第一位集合并且生成表示第一位组的第一充电电流。 第二流水线级包括第一GSHE MTJ元件。 第一GSHE MTJ元件被配置为设置第一逻辑运算的第一位状态，并且具有第一阈值电流电平。 第一GSHE MTJ元件被配置为响应于第一充电电流产生第一GSHE自旋电流。 以这种方式，第一GSHE MTJ元件还被配置为对第一位集执行第一逻辑运算。

公开(公告)号：US08779824B2

公开(公告)日：2014-07-15

申请号：US13716263

申请日：2012-12-17

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Kendrick H. Yuen ,  David W. Hansquine ,  Robert P. Gilmore ,  Jeff A. Levin

IPC: G06F1/04 ,  H03K3/00

CPC classification number: H03K3/59

Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Abstract translation: 时钟信号通过向芯片施加振荡磁场而分布在芯片上。 包括磁场传感器的本地时钟发生电路分布在芯片周围，并且耦合到芯片上的本地时钟电路。 磁场传感器可以包括响应于所施加的磁场，自由层的磁性取向在自由层平面中自由旋转的时钟磁隧道结（MTJ）。 随着自由层磁化旋转，MTJ电阻在高电阻值和低电阻值之间交替。 耦合到时钟MTJ的时钟产生电路感测由时钟MTJ的交流电阻引起的电压振荡。 时钟产生电路包括放大器，其将所感测的电压转换成本地时钟信号。

公开(公告)号：US20140167831A1

公开(公告)日：2014-06-19

申请号：US13716263

申请日：2012-12-17

Applicant: QUALCOMM INCORPORATED

Inventor： Wenqing Wu ,  Kendrick H. Yuen ,  David W. Hansquine ,  Robert P. Gilmore ,  Jeff A. Levin

IPC: H03K3/59

CPC classification number: H03K3/59

Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Abstract translation: 时钟信号通过向芯片施加振荡磁场而分布在芯片上。 包括磁场传感器的本地时钟发生电路分布在芯片周围，并且耦合到芯片上的本地时钟电路。 磁场传感器可以包括响应于所施加的磁场，自由层的磁性取向在自由层平面中自由旋转的时钟磁隧道结（MTJ）。 随着自由层磁化旋转，MTJ电阻在高电阻值和低电阻值之间交替。 耦合到时钟MTJ的时钟产生电路感测由时钟MTJ的交流电阻引起的电压振荡。 时钟产生电路包括放大器，其将所感测的电压转换成本地时钟信号。

公开(公告)号：US20140098602A1

公开(公告)日：2014-04-10

申请号：US14104443

申请日：2013-12-12

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Kendrick Hoy Leong Yuen ,  Xiaochun Zhu ,  Seung Hyuk Kang ,  Matthew Michael Nowak ,  Jeffrey Alexander Levin ,  Robert P. Gilmore ,  Nicholas Ka Ming Yu

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/54 ,  G11C11/5607

Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Abstract translation: 将概率编程电流注入到双稳定概率开关元件簇中，概率编程电流具有设置为导致任何给定双稳态开关元件切换的小于一概率的参数，以及bi的簇的电阻 - 检测到稳定的开关元件。 注入概率编程电流，并检测到簇状态的电阻，直到满足终止条件。 可选地，终止条件是以表示多位数据的值检测双稳态开关元件群的电阻。