公开(公告)号：US09252228B2

公开(公告)日：2016-02-02

申请号：US14093105

申请日：2013-11-29

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/70 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66651 ,  H01L21/28035 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

Abstract: A fully depleted silicon-on-insulator MOSFET transistor with reduced variation in threshold voltage. The substrate of the transistor is doped to form a ground plane below a buried oxide layer. A lightly doped channel is formed over the buried oxide layer. A gate dielectric of Silicon Oxynitride is formed over the channel, and a polysilicon gate is formed over the gate dielectric. The polysilicon gate is doped to have a work function not greater 4.2 electron volts for a p-type doped channel (for an n-channel MOSFET), and not less than 5.0 electron volts for an n-type doped channel (for a p-channel MOSFET). The thickness of the buried oxide layer and the channel need not be greater than 20 nanometers and 10 nanometers, respectively.

Abstract translation: 完全耗尽的绝缘体上硅MOSFET晶体管，其阈值电压变化较小。 掺杂晶体管的衬底以在掩埋氧化物层下方形成接地层。 在掩埋氧化物层上形成轻掺杂沟道。 在沟道上形成氮氧化硅的栅极电介质，并且在栅极电介质上形成多晶硅栅极。 对于p型掺杂沟道（对于n沟道MOSFET），多晶硅栅极被掺杂以具有不大于4.2电子伏特的功函数，对于n型掺杂沟道（对于p型掺杂沟道），功率不小于5.0电子伏特， 通道MOSFET）。 掩埋氧化物层和沟道的厚度不必分别大于20纳米和10纳米。

公开(公告)号：US20150035019A1

公开(公告)日：2015-02-05

申请号：US13956398

申请日：2013-08-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

Abstract: A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

Abstract translation: 形成不同材料的散热片的方法包括：提供具有顶表面的第一材料层的衬底，掩蔽衬底的第一部分，留下衬底的第二部分，蚀刻第二部分的第一开口，形成 在所述开口中的第二材料的主体到所述第一材料的所述层的顶表面的高度，去除所述掩模，以及在所述第一部分处形成所述第一材料的翅片，并在所述第二部分处形成所述第二材料的翅片 。 还公开了具有由至少两种不同材料形成的翅片的finFET器件。

公开(公告)号：US20140269020A1

公开(公告)日：2014-09-18

申请号：US13842263

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Stanley Seungchul Song ,  Zhongze Wang

IPC: G11C11/4074 ,  G06F17/50 ,  G11C14/00

CPC classification number: G11C11/4074 ,  G06F17/5072 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

Abstract: A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an operating voltage based on the temperature and based on fabrication data associated with the memory array. The method further includes regulating, at the voltage regulating device, a voltage provided to the memory array based on the operating voltage.

Abstract translation: 一种方法包括测量与存储器阵列相关联的传感器的温度。 该方法还包括在电压调节装置处基于温度和基于与存储器阵列相关联的制造数据来计算工作电压。 该方法还包括在电压调节装置处基于工作电压调节提供给存储器阵列的电压。

公开(公告)号：US11830819B2

公开(公告)日：2023-11-28

申请号：US17357811

申请日：2021-06-24

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Abinash Roy ,  Stanley Seungchul Song ,  Jonghae Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227

Abstract: A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：US20220375851A1

公开(公告)日：2022-11-24

申请号：US17324614

申请日：2021-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Stanley Seungchul Song ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L49/02

Abstract: Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed on an IC, in an ILM, to minimize the lengths of the power and ground traces coupling the DTCs to circuits in a semiconductor layer. The DTCs and the semiconductor layer are on opposite sides of the metal layer(s) used to interconnect the circuits, so the locations of the DTCs in the ILM can be independent of circuit layout and interconnect routing. IC dies with DTCs disposed in the ILM can significantly reduce voltage droop and spikes in IC dies in an IC stack. In one example, DTCs are also located in trenches in the substrate of the IC die.

公开(公告)号：US11437379B2

公开(公告)日：2022-09-06

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Deepak Sharma ,  Bharani Chava ,  Hyeokjin Lim ,  Peijie Feng ,  Seung Hyuk Kang ,  Jonghae Kim ,  Periannan Chidambaram ,  Kern Rim ,  Giridhar Nallapati ,  Venugopal Boynapalli ,  Foua Vang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/095 ,  H01L23/528 ,  H01L29/78 ,  H03K19/0185

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20220165707A1

公开(公告)日：2022-05-26

申请号：US17100060

申请日：2020-11-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Bharani Chava

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking. To facilitate providing additional electrical routing paths for die-to-die interconnections between stacked IC dice in the IC package, a BS-BEOL metallization structure of a first die of the stacked dice of the IC package is stacked adjacent to a FS-BEOL metallization structure of a second die of the stacked IC dice. Electrical routing paths for die-to-die interconnections between the stacked IC dice are provided from the BS-BEOL metallization structure of the first die to the FS-BEOL metallization structure of the second die. It may be more feasible to form shorter electrical routing paths in the thinner BS-BEOL metallization structure than in a FS-BEM metallization structure for lower-resistance and/or lower-capacitance die-to-die interconnections for faster and/or compatible performance of semiconductor devices in the IC dice.

公开(公告)号：US20210384310A1

公开(公告)日：2021-12-09

申请号：US16893993

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Jun Yuan ,  Peijie Feng ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234

Abstract: Gate-all-around (GAA) transistors with an additional bottom channel for reduced parasitic capacitance and methods of fabricating the same include one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire or nanoslab semiconductors, are surrounded by gate material. The GAA transistor further includes an additional semiconductor channel between a bottom section of a gate material and a silicon on insulator (SOI) substrate in a GAA transistor. This additional channel, sometimes referred to as a bottom channel, may be thinner than other channels in the GAA transistor and may have a thickness less than its length.

公开(公告)号：US10996261B2

公开(公告)日：2021-05-04

申请号：US16186623

申请日：2018-11-12

Applicant: QUALCOMM Incorporated

Inventor： Hyunwoo Park ,  Youn Sung Choi ,  Stanley Seungchul Song

IPC: G01R31/26

Abstract: Aspects generally relate methods and apparatuses of gate leakage detection of a transistor. A gate pad is coupled to a gate of a MOS transistor. A gate leakage detection circuit is coupled to the gate pad, wherein the gate leakage detection circuit is configured to estimate a gate leakage current. Based on the estimated gate leakage current determining a quality of a gate fabrication process.

公开(公告)号：US10325979B1

公开(公告)日：2019-06-18

申请号：US15860005

申请日：2018-01-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing Bao ,  Jun Chen ,  Yangyang Sun ,  Stanley Seungchul Song ,  Giridhar Nallapati

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.