公开(公告)号：US11502053B2

公开(公告)日：2022-11-15

申请号：US17103834

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal ,  David A. Daycock

IPC: H01L23/00 ,  H01L25/18

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

公开(公告)号：US11322516B2

公开(公告)日：2022-05-03

申请号：US17007951

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L27/11582 ,  H01L21/762 ,  H01L29/06

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US20210408029A1

公开(公告)日：2021-12-30

申请号：US17473679

申请日：2021-09-13

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/11573 ,  H01L21/762 ,  H01L27/11578 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11575

Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

公开(公告)号：US11121146B2

公开(公告)日：2021-09-14

申请号：US16159955

申请日：2018-10-15

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/11573 ,  H01L27/11578 ,  H01L21/768 ,  H01L21/762 ,  H01L27/1157 ,  H01L27/11575

Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

公开(公告)号：US20210242131A1

公开(公告)日：2021-08-05

申请号：US16778346

申请日：2020-01-31

Applicant: Micron Technology, Inc.

Inventor： Biow Hiem Ong ,  David A. Daycock ,  Chieh Hsien Quek ,  Chii Wean Calvin Chen ,  Christian George Emor ,  Wing Yu Lo

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11556

Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.

公开(公告)号：US10658380B2

公开(公告)日：2020-05-19

申请号：US16160146

申请日：2018-10-15

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  Anilkumar Chandolu ,  Indra V. Chary ,  Darwin A. Clampitt ,  Gordon Haller ,  Thomas George ,  Brett D. Lowe ,  David A. Daycock

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11573

Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

公开(公告)号：US20140374811A1

公开(公告)日：2014-12-25

申请号：US13921509

申请日：2013-06-19

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  David A. Daycock ,  Kunal Shrotri

IPC: H01L21/308 ,  H01L27/115 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/42324 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/788

Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control region.

Abstract translation: 形成半导体器件，存储器单元和存储器单元阵列的方法包括在导电材料上形成衬垫并将衬套暴露于自由基氧化工艺以使衬垫致密化。 致密的衬垫可以保护导电材料在随后的图案化工艺期间免受实质的劣化或损坏。 根据本公开的实施例的半导体器件结构包括从衬底延伸并由暴露衬底的一部分的沟槽间隔开的特征。 衬垫设置在每个特征中的至少一个导电材料的区域的侧壁上。 根据本公开的实施例的半导体器件包括存储器单元，每个存储器单元包括控制栅极区域和在控制区域下具有基本对准侧壁和电荷结构的封盖区域。

公开(公告)号：US20140159132A1

公开(公告)日：2014-06-12

申请号：US13706532

申请日：2012-12-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Daycock ,  Matthew J. King ,  Christopher J. Larsen

IPC: H01L29/51 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4991

Abstract: Memory arrays and their formation are disclosed. The formation of one such memory array includes forming first and second spacers respectively adjacent to sidewalls of first and second conductors so that the first and second spacers extend into an opening between the first and second conductors and terminate above bottoms of the first and second conductors, and closing the opening with a material that extends between the first and second spacers so that an air gap is formed in the closed opening.

Abstract translation: 公开了存储器阵列及其形成。 一个这样的存储器阵列的形成包括分别与第一和第二导体的侧壁相邻地形成第一和第二间隔物，使得第一和第二间隔物延伸到第一和第二导体之间的开口中并终止在第一和第二导体的底部之上， 并且用在第一和第二间隔件之间延伸的材料封闭开口，使得在封闭的开口中形成气隙。