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    Diplexer and Transceiver thereof
    21.
    发明申请
    Diplexer and Transceiver thereof 有权
    双工器及其收发器

    公开(公告)号：US20140233441A1

    公开(公告)日：2014-08-21

    申请号：US14139806

    申请日：2013-12-23

    Applicant: MEDIATEK INC.

    Inventor： Chih-Hung Lee ,  Ming-Da Tsai ,  Jui-Lin Hsu

    IPC: H04L5/06

    CPC classification number: H03H7/463 ,  H03H7/09 ,  H04B1/005

    Abstract: A diplexer, for coupling a first radio frequency (RF) signal corresponding to a first carrier frequency and a second RF signal corresponding to a second carrier frequency is disclosed. The diplexer includes a first port arranged to couple the first RF signal; a second port arranged to couple the second RF signal; a third port capable of connecting an antenna; a first impedance unit coupled to the first port and the third port; and a second impedance unit coupled to the second port and the third port; wherein the first port, the second port and the third port are coupled to a direct current (DC) ground; wherein the first impedance unit is arranged to provide an first open-circuit impedance against the second RF signal, and the second impedance unit is arranged to provide a second open-circuit impedance against the first RF signal.

    Abstract translation: 公开了一种用于耦合对应于第一载波频率的第一射频（RF）信号和对应于第二载波频率的第二RF信号的双工器。 双工器包括被布置成耦合第一RF信号的第一端口; 布置成耦合第二RF信号的第二端口; 能够连接天线的第三端口; 耦合到所述第一端口和所述第三端口的第一阻抗单元; 以及耦合到所述第二端口和所述第三端口的第二阻抗单元; 其中所述第一端口，所述第二端口和所述第三端口耦合到直流（DC）接地; 其中所述第一阻抗单元布置成针对所述第二RF信号提供第一开路阻抗，并且所述第二阻抗单元布置成针对所述第一RF信号提供第二开路阻抗。

    METHOD FOR CONTROLLING ELECTRICAL PROPERTY OF PASSIVE DEVICE DURING FABRICATION OF INTEGRATED COMPONENT AND RELATED INTEGRATED COMPONENT
    27.
    发明申请
    METHOD FOR CONTROLLING ELECTRICAL PROPERTY OF PASSIVE DEVICE DURING FABRICATION OF INTEGRATED COMPONENT AND RELATED INTEGRATED COMPONENT 有权
    一体化组件制造过程中被动设备电气性能及相关集成组件的方法

    公开(公告)号：US20140035096A1

    公开(公告)日：2014-02-06

    申请号：US13797992

    申请日：2013-03-12

    Applicant: MEDIATEK INC.

    Inventor： Ming-Da Tsai ,  George Chien ,  Cheng-Chou Hung

    IPC: H01L21/66

    CPC classification number: H01L22/14 ,  H01L22/20

    Abstract: A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component.

    Abstract translation: 一种用于在集成部件的制造期间控制无源器件的电性能的方法包括提供衬底，在衬底上制造无源器件，测量无源器件的电性能以获得测量结果，确定至少一个布局 通过用于调整无源器件的电性能的测量结果对应于至少一个后续制造过程的模式，以及继续包括集成部件的至少一个后续制造过程的其余的制造。

    Frequency divider for generating output clock signal with duty cycle different from duty cycle of input clock signal
    28.
    发明授权
    Frequency divider for generating output clock signal with duty cycle different from duty cycle of input clock signal 有权
    用于产生输出时钟信号的分频器，占空比不同于输入时钟信号的占空比

    公开(公告)号：US08502573B2

    公开(公告)日：2013-08-06

    申请号：US13658809

    申请日：2012-10-23

    Applicant: Mediatek Inc.

    Inventor： Ming-Da Tsai

    IPC: H03K21/00

    CPC classification number: H03K23/425 ,  G06F1/08 ,  H03K3/356173 ,  H03K21/023 ,  H03K21/10

    Abstract: A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle. Each of the logic circuit blocks includes a plurality of first transistors coupled in parallel between a first reference voltage and an output terminal, and a plurality of second transistors coupled in series between a second reference voltage and the output terminal.

    Abstract translation: 分频器包括多个逻辑电路块。 每个逻辑电路块具有多个控制端子。 一个逻辑电路块的控制端中的至少一个被布置成接收具有第一占空比的输入时钟信号。 逻辑电路块中的一个的剩余控制端中的至少一个被布置成通过正反馈耦合另一个逻辑电路块。 所述剩余控制端中的至少一个的时钟信号具有与第一占空比不同的第二占空比。 每个逻辑电路块包括并联在第一参考电压和输出端之间的多个第一晶体管，以及串联耦合在第二参考电压和输出端之间的多个第二晶体管。

    PHASE-ROTATED HARMONIC-REJECTION MIXER APPARATUS
    29.
    发明申请
    PHASE-ROTATED HARMONIC-REJECTION MIXER APPARATUS 审中-公开

    公开(公告)号：US20170294878A1

    公开(公告)日：2017-10-12

    申请号：US15462923

    申请日：2017-03-20

    Applicant: MEDIATEK INC.

    Inventor： Chien-Wei Tseng ,  Ian Tseng ,  Ming-Da Tsai ,  Yangjian Chen ,  Chien-Cheng Lin

    IPC: H03D7/12

    CPC classification number: H03D7/12 ,  H03D7/165 ,  H03D2200/0082

    Abstract: A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

    Radio frequency transmitter, power combiners and terminations therefor
    30.
    发明授权
    Radio frequency transmitter, power combiners and terminations therefor 有权

    公开(公告)号：US09722571B2

    公开(公告)日：2017-08-01

    申请号：US14140519

    申请日：2013-12-25

    Applicant: MEDIATEK INC.

    Inventor： Ming-Da Tsai

    IPC: H03H7/48 ,  H04B1/04 ,  H01F19/04

    CPC classification number: H03H7/48 ,  H01F19/04 ,  H04B1/0458

    Abstract: A power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding; wherein, the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding. In addition, there is provided a radio frequency (RF) transmitter having a power combiner, where the power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding, wherein the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding.

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