公开(公告)号：US11839070B1

公开(公告)日：2023-12-05

申请号：US17553511

申请日：2021-12-16

申请人： Kepler Computing Inc.

发明人： Noriyuki Sato ,  Niloy Mukherjee ,  Mauricio Manfrini ,  Tanay Gosavi ,  Rajeev Kumar Dokania ,  Somilkumar J. Rathi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： H01L21/00 ,  H10B53/20 ,  G11C11/22 ,  H01L23/31 ,  G11C5/02 ,  H01L49/02 ,  H01L23/538

CPC分类号： H10B53/20 ,  G11C5/025 ,  G11C11/221 ,  H01L23/31 ,  H01L23/5384 ,  H01L28/75

摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

公开(公告)号：US11810608B1

公开(公告)日：2023-11-07

申请号：US18061270

申请日：2022-12-02

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  G11C11/417 ,  G11C5/10 ,  H10B53/10 ,  H10B53/20

CPC分类号： G11C11/221 ,  G11C5/10 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2293 ,  G11C11/417 ,  H10B53/10 ,  H10B53/20

摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

公开(公告)号：US11800722B1

公开(公告)日：2023-10-24

申请号：US17517948

申请日：2021-11-03

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/00 ,  H10B53/30 ,  H10B53/40

CPC分类号： H10B53/30 ,  H10B53/40

摘要： To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

公开(公告)号：US20230301113A1

公开(公告)日：2023-09-21

申请号：US17655422

申请日：2022-03-18

申请人： Kepler Computing Inc.

发明人： Noriyuki Sato ,  Tanay Gosavi ,  Rafael Rios ,  Amrita Mathuriya ,  Niloy Mukherjee ,  Mauricio Manfrini ,  Rajeev Kumar Dokania ,  Somilkumar J. Rathi ,  Sasikanth Manipatruni

IPC分类号： H01L27/11507

CPC分类号： H01L27/11507

摘要： A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

公开(公告)号：US11765908B1

公开(公告)日：2023-09-19

申请号：US18167816

申请日：2023-02-10

申请人： Kepler Computing Inc.

发明人： Mauricio Manfrini ,  Noriyuki Sato ,  James David Clarkson ,  Abel Fernandez ,  Somilkumar J. Rathi ,  Niloy Mukherjee ,  Tanay Gosavi ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H10B53/30

CPC分类号： H10B53/30

摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

公开(公告)号：US11751403B1

公开(公告)日：2023-09-05

申请号：US17516526

申请日：2021-11-01

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C16/04 ,  H10B53/30 ,  H10B53/40 ,  G11C11/404

CPC分类号： H10B53/30 ,  G11C11/404 ,  H10B53/40

摘要： To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

公开(公告)号：US20230246063A1

公开(公告)日：2023-08-03

申请号：US17649665

申请日：2022-02-01

申请人： Kepler Computing Inc.

发明人： Niloy Mukherjee ,  Somilkumar J. Rathi ,  Jason Y. Wu ,  Pratyush Pandey ,  Zeying Ren ,  FNU Atiquzzaman ,  Gabriel Antonio Paulius Velarde ,  Noriyuki Sato ,  Mauricio Manfrini ,  Tanay Gosavi ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Ramamoorthy Ramesh ,  Sasikanth Manipatruni

IPC分类号： H01L49/02 ,  H01L21/324 ,  H01L21/768 ,  H01L27/11507 ,  H01L45/00

CPC分类号： H01L28/57 ,  H01L21/324 ,  H01L21/76832 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75 ,  H01L45/147

摘要： A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

公开(公告)号：US11696450B1

公开(公告)日：2023-07-04

申请号：US17516577

申请日：2021-11-01

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C16/04 ,  H10B53/20 ,  G11C11/22 ,  H01L49/02 ,  H01L21/02 ,  G11C11/404 ,  H10B12/00

CPC分类号： H10B53/20 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/4045 ,  H01L21/02197 ,  H01L28/56 ,  H10B12/056 ,  H10B12/36

摘要： To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

公开(公告)号：US20230187476A1

公开(公告)日：2023-06-15

申请号：US17550904

申请日：2021-12-14

申请人： Kepler Computing Inc.

发明人： Noriyuki Sato ,  Niloy Mukherjee ,  Mauricio Manfrini ,  Tanay Gosavi ,  Rajeev Kumar Dokania ,  Somilkumar J. Rathi ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： H01L49/02 ,  H01L27/11507

CPC分类号： H01L28/57 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75 ,  G11C11/221

摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

公开(公告)号：US20230070073A1

公开(公告)日：2023-03-09

申请号：US17485161

申请日：2021-09-24

申请人： Kepler Computing, Inc.

发明人： Noriyuki Sato ,  Tanay Gosavi ,  Niloy Mukherjee ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H01L27/11507 ,  H01L27/11514 ,  H03K19/185 ,  H01L23/538 ,  H01L49/02

摘要： A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.