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21.发明授权Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures 有权用于高压引脚ESD保护的双向背对背堆叠SCR，制造和设计结构的方法公开(公告)号：US08760831B2
公开(公告)日：2014-06-24
申请号：US13762948
申请日：2013-02-08
发明人： Michel J. Abou-Khalil , Robert J. Gauthier , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/04 , H01L29/66 , H01L27/02 , H01L29/747 , H01L29/87
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87 , H02H9/04
摘要： Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode of a first of the back-to-back stacked SCR is connected to an input. An anode of a second of the back-to-back stacked SCR is connected to ground. Cathodes of the first and second of the back-to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively and deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.
摘要翻译： 提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。 该器件包括对称双向背对背层叠可控硅整流器（SCR）。 背对背堆叠的SCR中的第一个的阳极连接到输入。 背对背堆叠的SCR的第二个的阳极连接到地面。 第一个和第二个背靠背堆叠的SCR的阴极连接在一起。 对称双向背靠背SCR中的每一个包括一对二极管，其引导电流朝向阴极，其在施加电压时有效地变得有效地反向偏置，并且从对称的双向后向SCR中的一个去激活元件， 另一个对称双向背对背SCR的二极管在与反向偏置二极管相同的方向上直流电流，反向SCR。
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公开(公告)号：US08674400B2
公开(公告)日：2014-03-18
申请号：US13743392
申请日：2013-01-17
IPC分类号： H01L29/74
CPC分类号： H01L29/66068 , H01L29/66393 , H01L29/7436
摘要： A latchup silicon controlled rectifier (SCR) includes a p+ region and an n+ region located in a p-well of the latchup SCR; and a p+ region and an n+ region located in a n-well of the latchup SCR, wherein the latchup SCR further comprises one of embedded silicon germanium (eSiGe) in the p+ region in the n-well of the latchup SCR and silicon carbide (SiC) in the n+ region in the p-well of the latchup SCR.
摘要翻译： 闭锁可控硅整流器（SCR）包括位于闭锁SCR的p阱中的p +区和n +区; 以及位于所述闭锁SCR的n阱中的p +区域和n +区域，其中所述闭锁SCR还包括所述闭锁SCR的n阱中的p +区域中的嵌入硅锗（eSiGe）中的一种和碳化硅（ SiC）在闭锁SCR的p阱中的n +区域中。
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公开(公告)号：US20140033519A1
公开(公告)日：2014-02-06
申请号：US14054033
申请日：2013-10-15
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L25/065 , H01L21/66
CPC分类号： H01L22/30 , H01L21/76886 , H01L21/76898 , H01L22/14 , H01L22/20 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , Y10T29/5313 , Y10T29/532 , H01L2924/00
摘要： Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.
摘要翻译： 用于改变布线路径的电阻的方法和系统。 将布线路径的电阻与目标电阻值进行比较。 如果布线路径的电阻超过目标电阻值，则选择性地向布线路径施加电流，以物理地改变布线路径的一部分。 可以选择电流来改变布线路径，使得电阻下降到小于或等于目标电阻值的值。
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公开(公告)号：US10755949B2
公开(公告)日：2020-08-25
申请号：US16016920
申请日：2018-06-25
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Robert R. Robison
IPC分类号： H01L23/62 , H01L21/324 , H01L29/866 , H01L27/02 , H01L29/861
摘要： Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
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公开(公告)号：US10224710B2
公开(公告)日：2019-03-05
申请号：US15815473
申请日：2017-11-16
IPC分类号： H02H9/00 , H02H9/04 , H01L23/522 , H01L27/02 , H01L29/94
摘要： An electrostatic discharge protection circuit includes a power clamp device, a timing circuit including a first resistor, a first capacitor that is connected with the first resistor at a first node, and a second capacitor that is connected to a second node, a logic gate including a first input connected with the first node, a second input connected with the second node, and an output connected with the power clamp device, and a decoder device connected with a first address pin and a second address pin. The first address pin and the second address pin are used to detect the power clamp device switching on at time of power on and draining current.
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公开(公告)号：US20180097358A1
公开(公告)日：2018-04-05
申请号：US15815464
申请日：2017-11-16
IPC分类号： H02H9/04 , H01L27/02 , H01L23/522 , H01L29/94
CPC分类号： H02H9/046 , H01L23/5228 , H01L27/0285 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection circuit includes a transistor device, a first timing circuit including a first resistor and a first capacitor that is connected with the first resistor at a first node, a second timing circuit including a second resistor and a second capacitor that is connected with the second resistor at a second node, and a logic gate including a first input connected with the first node, a second input coupled with the second node, and an output connected with the transistor device.
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公开(公告)号：US09397086B2
公开(公告)日：2016-07-19
申请号：US14824560
申请日：2015-08-12
CPC分类号： H01L27/0262 , G06F17/5072 , H01L21/8249 , H01L21/845 , H01L27/0255 , H01L27/06 , H01L27/1211 , H01L29/06
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
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公开(公告)号：US09349838B2
公开(公告)日：2016-05-24
申请号：US14530034
申请日：2014-10-31
发明人： Kangguo Cheng , Balasubramanian Pranatharthi Haran , Junjun Li , Shom Ponoth , Theodorus Eduardus Standaert , Tenko Yamashita
IPC分类号： H01L29/66 , H01L29/861 , H01L29/40 , H01L29/423 , H01L27/02 , H01L23/367 , H01L23/373 , H01L29/06 , H01L27/12
CPC分类号： H01L29/66795 , H01L23/367 , H01L23/3738 , H01L27/0255 , H01L27/1203 , H01L27/1211 , H01L29/0603 , H01L29/402 , H01L29/423 , H01L29/42376 , H01L29/6609 , H01L29/66742 , H01L29/861 , H01L29/8613 , H01L2924/0002 , H01L2924/00
摘要： Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.
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公开(公告)号：US20150348960A1
公开(公告)日：2015-12-03
申请号：US14290141
申请日：2014-05-29
发明人： Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , You Li , Souvick Mitra
CPC分类号： H01L27/0266 , H01G13/00 , H01G17/00 , H01L23/5256 , H01L27/0285 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from electrostatic discharge. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, and a power clamp device coupled with the timing circuit at the node. The capacitor includes a plurality of capacitor elements. The protection circuit further includes a plurality of electronic fuses. Each electronic fuse is coupled with a respective one of the capacitor elements. A field effect transistor may be coupled in parallel with the resistor of the timing circuit, and may be used to bypass the resistor to provide a programming current to any electronic fuse coupled with a capacitor element of abnormally low impedance.
摘要翻译： 制造提供静电放电保护的电路的电路和方法，以及保护集成电路免受静电放电的方法。 保护电路可以包括功率钳位装置，包括电阻器的定时电路和与节点处的电阻器耦合的电容器，以及与节点处的定时电路耦合的功率钳位装置。 电容器包括多个电容器元件。 保护电路还包括多个电子保险丝。 每个电子熔断器与相应的一个电容器元件耦合。 场效应晶体管可以与定时电路的电阻并联耦合，并且可以用于旁路电阻器以向与异常低阻抗的电容器元件耦合的任何电子熔丝提供编程电流。
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公开(公告)号：US20150288174A1
公开(公告)日：2015-10-08
申请号：US14243295
申请日：2014-04-02
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/04
摘要： Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.
摘要翻译： 提供静电放电保护的电路和方法。 保护电路可以包括功率钳位装置，包括电阻器的定时电路和与节点处的电阻器耦合的电容器，被配置为选择性地将定时电路的节点与电源钳位装置连接的传输门，以及 控制电路与节点耦合。 控制电路被配置为基于电容器是否有缺陷来控制传输门。 如果定时电路中的电容器有故障并且相关的芯片被供电，则定时电路可以被去激活。 或者，如果定时电路中的电容器没有故障，则定时电路可以被激活。
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