公开(公告)号：US09362283B2

公开(公告)日：2016-06-07

申请号：US14793005

申请日：2015-07-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/092 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.

Abstract translation: 集成电路产品包括具有栅极结构的NMOS晶体管，该栅极结构包括NMOS栅绝缘层，位于NMOS栅绝缘层上的第一NMOS金属层，位于第一NMOS金属层上方的NMOS金属硅化物材料， 位于NMOS栅极绝缘层上方并与NMOS栅绝缘层接触的第二金属材料，第一NMOS金属层和NMOS金属硅化物层。 PMOS晶体管具有栅极结构，其包括PMOS栅极绝缘层，位于PMOS栅极绝缘层上的第一PMOS金属层，位于第一PMOS金属层上方的PMOS金属硅化物材料和位于第一PMOS金属层上方的第二金属材料层 并且与PMOS栅绝缘层，第一PMOS金属层和PMOS金属硅化物层接触。

公开(公告)号：US09287180B2

公开(公告)日：2016-03-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

公开(公告)号：US20150214345A1

公开(公告)日：2015-07-30

申请号：US14164368

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jinping Liu ,  Churamani Gaire ,  Mariappan Hariharaputhiran ,  Andy Chih-Hung Wei ,  Bharat V. Krishnan ,  Cuiqin Xu ,  Michael Ganz

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/88 ,  H01L29/73 ,  H01L21/306 ,  H01L29/161 ,  H01L29/06 ,  H01L29/51 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66151 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/66977 ,  H01L29/7311 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/88

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.

Abstract translation: 提供了用于在集成电路（IC）器件（例如，金属氧化物半导体场效应晶体管（MOSFET））中隔离源极和漏极区域的方法。 具体地，该器件包括形成在衬底上的栅极结构，与栅极结构相邻嵌入在衬底内的源极和漏极（S / D）以及S / D和衬底之间的衬里层（例如，硅 - 碳） 。 在一种方法中，衬垫层也形成在S / D的顶部。 因此，形成在接合部中的衬垫层防止掺杂剂从源极/漏极扩散。

公开(公告)号：US09093476B2

公开(公告)日：2015-07-28

申请号：US13954289

申请日：2013-07-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括：具有第一侧，第二侧，暴露的第一端面和暴露的第二端面的翅片结构的沟道区。 形成在沟道区域的第一侧和第二侧上方的栅极。 该方法包括通过暴露的第一端表面和暴露的第二端表面将离子注入沟道区域。 此外，所述方法包括在所述通道区域的暴露的第一端面和暴露的第二端面附近形成所述鳍结构的源极/漏极区域。

公开(公告)号：US20190326209A1

公开(公告)日：2019-10-24

申请号：US15959727

申请日：2018-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L23/525 ,  H01L21/768

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US10453936B2

公开(公告)日：2019-10-22

申请号：US15797837

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a sacrificial gate electrode material, performing a first gate-cut etching process to thereby form an opening in the sacrificial gate electrode material and forming an internal sidewall spacer in the opening. In this example, the method also includes, after forming the internal sidewall spacer, performing a second gate-cut etching process through the opening, the second gate-cut etching process being adapted to remove the sacrificial gate electrode material, performing an oxidizing anneal process and forming an insulating material in at least the opening.

公开(公告)号：US10403742B2

公开(公告)日：2019-09-03

申请号：US15712748

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US10008456B1

公开(公告)日：2018-06-26

申请号：US15469983

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Man Gu ,  Jinping Liu

IPC: H01L23/58 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/60

CPC classification number: H01L21/28141 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L29/6656 ,  H01L2021/6009

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. First and second spacers are formed adjacent to a surface of a device component from respective conformal layers. The first spacer is positioned between the surface of the device component and the second spacer. The second spacer includes a plurality of first lamina and a plurality of second lamina that are arranged in an alternating sequence with the first lamina. The first spacer has a first dielectric constant, and the second spacer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US09947769B1

公开(公告)日：2018-04-17

申请号：US15363461

申请日：2016-11-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6656 ,  H01L21/0214 ,  H01L21/0228 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer is located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer is located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US09905472B1

公开(公告)日：2018-02-27

申请号：US15440072

申请日：2017-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Jinping Liu ,  Haifeng Sheng

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/088 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L21/823475 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41725

Abstract: A method of removing the CESL from small canyon TS structures of a MOSFET device while maintaining gate cap height and the resulting device are provided. Embodiments include providing two gates laterally separated over and perpendicular to a fin of a semiconductor device, each gate having sidewall spacers and a nitride cap; forming a conformal SiN CESL on bottom and side surfaces of a trench formed between opposing spacers between the gates; filling the trench with oxide; planarizing the spacers, nitride caps, oxide, and CESL; removing the oxide; forming a topological flat-SiN layer over the spacers, nitride caps, and CESL; removing the topological flat-SiN layer from side and bottom surfaces of the trench; removing the CESL and the topological flat-SiN layer down to a top surface of the spacers; and performing contact metallization.