公开(公告)号：US10008456B1

公开(公告)日：2018-06-26

申请号：US15469983

申请日：2017-03-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Tao Han ,  Man Gu ,  Jinping Liu

IPC分类号： H01L23/58 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/60

CPC分类号： H01L21/28141 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L29/6656 ,  H01L2021/6009

摘要： Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. First and second spacers are formed adjacent to a surface of a device component from respective conformal layers. The first spacer is positioned between the surface of the device component and the second spacer. The second spacer includes a plurality of first lamina and a plurality of second lamina that are arranged in an alternating sequence with the first lamina. The first spacer has a first dielectric constant, and the second spacer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20210020515A1

公开(公告)日：2021-01-21

申请号：US16515638

申请日：2019-07-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Bingwu Liu ,  Tao Chu ,  Man Gu

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

摘要： One illustrative method disclosed herein includes forming at least one fin, forming a first recessed layer of insulating material adjacent the at least one fin and forming epi semiconductor material on the at least one fin. In this example, the method also includes forming a second recessed layer of insulating material above the first recessed layer of insulating material, wherein at least a portion of the epi semiconductor material is positioned above a level of the upper surface of the second recessed layer of insulating material, and forming a source/drain contact structure above the second recessed layer of insulating material, wherein the source/drain contact structure is conductively coupled to the epi semiconductor material.

公开(公告)号：US10777463B2

公开(公告)日：2020-09-15

申请号：US16247761

申请日：2019-01-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Man Gu ,  Tao Han

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

摘要： One illustrative device disclosed herein includes an epi cavity formed in a semiconductor substrate adjacent a gate structure of a transistor and an epi semiconductor material comprising first and second portions. The first portion of the epi semiconductor material is positioned within the epi cavity. The second portion of the epi semiconductor material is positioned above the first portion of the epi semiconductor material and above a level corresponding to a level of an upper surface of the semiconductor substrate. The first portion of the epi semiconductor material has a first dimension in a direction corresponding to a gate length direction of the transistor and the second portion of the epi semiconductor material has a second dimension in a direction corresponding to the gate length direction of the transistor, wherein the first dimension is greater than the second dimension.

公开(公告)号：US20200227320A1

公开(公告)日：2020-07-16

申请号：US16247761

申请日：2019-01-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Man Gu ,  Tao Han

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

摘要： One illustrative device disclosed herein includes an epi cavity formed in a semiconductor substrate adjacent a gate structure of a transistor and an epi semiconductor material comprising first and second portions. The first portion of the epi semiconductor material is positioned within the epi cavity. The second portion of the epi semiconductor material is positioned above the first portion of the epi semiconductor material and above a level corresponding to a level of an upper surface of the semiconductor substrate. The first portion of the epi semiconductor material has a first dimension in a direction corresponding to a gate length direction of the transistor and the second portion of the epi semiconductor material has a second dimension in a direction corresponding to the gate length direction of the transistor, wherein the first dimension is greater than the second dimension.

公开(公告)号：US20200287019A1

公开(公告)日：2020-09-10

申请号：US16296769

申请日：2019-03-08

申请人： GLOBALFOUNDRIES Inc.

发明人： George R. Mulfinger ,  Hong Yu ,  Man Gu ,  Jianwei Peng ,  Michael Aquilino

IPC分类号： H01L29/66 ,  H01L29/78

摘要： Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US10755918B2

公开(公告)日：2020-08-25

申请号：US16193313

申请日：2018-11-16

申请人： GLOBALFOUNDRIES INC.

发明人： Man Gu ,  Tao Han ,  Charlotte D. Adams

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a spacer with laminate liner and methods of manufacture. The structure includes: a replacement metal gate structure; a laminate low-k liner on the replacement metal gate structure; and a spacer on the laminate low-k liner.

公开(公告)号：US10192791B1

公开(公告)日：2019-01-29

申请号：US15913547

申请日：2018-03-06

申请人： GLOBALFOUNDRIES Inc.

发明人： Man Gu ,  Tao Han ,  Junsic Hong ,  Jiehui Shu ,  Asli Sirman ,  Charlotte Adams ,  Jinping Liu ,  Keith Tabakman

IPC分类号： H01L21/8242 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092

摘要： A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.